Implementing a Function to Switch Standard VGA Video Modes

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Implementing a Function to Switch Standard VGA Video Modes

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INDEX: Switching Standard VGA Modes Without the BIOS
I need a fully standard function as a default configuration entry point for the VGA, which takes 3 parameters to replace the BIOS services to switch video mode:

- VGA Register values or NULL (0)
- 256-color palette or NULL (0)
- Default text-mode font or NULL (0)


All of those structures must contain their size at the start in a 16-bit WORD, which contains the size of the structure including that WORD.

As we can see, we can tweak this function so that only non-null parameters cause an action in their respective area (switching video mode, loading a palette and/or loading a default text font). If they are null, we won't do anything, so we could use this same function only for 1 or several of these configuration tasks.



To be able to put together that function, I mostly only need functions to read and write the Attribute, CRTC, General, Graphics and Sequencer registers with those of the provided standard register set structure. I mainly need functions that know how to read or write to a full array of indexed registers. It looks like unless I really need to read or write individual indexed registers, and I know for what, I won't know how to implement that.

But when I implement individual routines for the different indexed or individual registers, I will do it in a level that denotes that those functions are NOT to control registers or controllers inside the VGA, but instead they provide functionality to make use of a VGA function.


I will also need a few functions to control fine-grained functionality through the different existing registers and bits of the VGA.

So I need the register values for modes 3h, 4h, 12h, 13h and Mode X, which are the most used ones. I might try to find information for other modes.

I need to put together extremely well-commented structures with the register values for the VGA so it serves as a good tutorial.

It seems that only text modes need a default font when we enter them, and also, only 256-color modes require that we specify a good palette to switch them.



Table of Contents

Text Mode 3h Configuration (80x25x16-Color EGA)
Mode 3h: Register Set Values
Mode 3h: 256-Color Palette
Mode 3h: Default Text Font


Graphics Mode 4h Configuration (320x200x4-Color CGA)
Mode 4h: Register Set Values
Mode 4h: 256-Color Palette
Mode 4h: Default Text Font (Not Present)


Graphics Mode 12h Configuration (640x480x16-Color VGA)
Mode 12h: Register Set Values
Mode 12h: 256-Color Palette
Mode 12h: Default Text Font (Not Present)


Graphics Mode 13h Configuration (320x200x256-Color MCGA)
Mode 13h: Register Set Values
Mode 13h: 256-Color Palette
Mode 13h: Default Text Font (Not Present)


Graphics Mode X Configuration (320x240x256-Color MCGA)
Mode X: Register Set Values
Mode X: 256-Color Palette
Mode X: Default Text Font (Not Present)


Making Use of the Configuration Information Blocks
Configuration Write Sequence for the Main VGA Register Set
Writing the Indexed Registers in the Four Controllers Embedded in the VGA
Turning the VGA Monitor On and Off
Enabling the 16-Color VGA Palette
Making the CRTC Controller Registers Writable
Last edited by ~ on Wed May 25, 2016 12:32 am, edited 16 times in total.
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Register Values for Mode 3h (Registers)

Post by ~ »

Register Values, Mode 3h, Text, 80x25x16 Colors, EGA

Code: Select all

;Version 2013-03-10
;;

EGA_Text_80x25x16Gen__MiscOutputReg:
;General Register, Miscellaneous Output (W; 0x3C2):
;;
 ;
 ;  Bits:
 ;      0 -- I/O Address select
 ;           Color Emulation  (1) or Monochrome Emulation   (0)
 ;
 ;      1 -- Enable RAM
 ;           Enable video RAM (1) or Disable address decode (0)
 ;
 ;    2,3 -- Clock Select - ??? - I currently don't know where is the CS2 bit
 ;                                so I don't know what configuration is selected here
 ;           CS2  CS1  CS0  Clock
 ;           ---  ---  ---  -----
 ;            0    0    0   25.175 MHz    ;<--this one!!!!!!!
 ;            0    0    1   28.322 MHz
 ;         -------------------------------Below this line, consider Oak-specific values
 ;            0    1    0   65 MHz (external clock per true VGA standard)
 ;            0    1    1   44.9 MHz (undefined per true VGA standard)
 ;            1    0    0   14.161 MHz (derived from 28.322 MHz)
 ;            1    0    1   18 MHz (derived from 36 MHz)
 ;            1    1    0   40 MHz
 ;            1    1    1   36 MHz
 ;
 ;      4 -- Reserved
 ;            (0)
 ;
 ;      5 -- Page bit for odd/even
 ;           High 64K         (1) or Low 64K                (0) page of memory
 ;
 ;      6 -- Horizontal Sync Polarity
 ;           Negative         (1) or Posite Vertic. Retrace (0)
 ;
 ;      7 -- Vertical Sync Polarity
 ;           Positive         (0) or Negative Vert. Retrace (0)
 ;
 ;      Bits 7-6
 ;      --------
 ;            00 -- reserved
 ;            01 -- 400 lines     ;<-- This one!
 ;            10 -- 350 lines
 ;            11 -- 480 lines
 ;
 ;
 ;
 ;
 ;
 ;;
;  db 01100111b       ;0x67
db 0x67









EGA_Text_80x25x16Gen__FeatureControlReg:
;General Register, Feature Control (RW; 0x3DA color; 0x3BA mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      3 -- Vertical Sync Select
 ;           Normal (0) or Logical OR of Vertical Sync End/Vertical Display Enable (1)
 ;
 ;      All other bits are Reserved
 ;
 ;;
;  db 00000000b       ;0x00
db 4h



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EGA_Text_80x25x16SequencerRegs:
;Sequencer Register, Index 0, Reset Register (RW; 0x3C4=0; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Asynchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      1 -- Synchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      All other bits are reserved
 ;;
  db 00000011b       ;0x03










;Sequencer Register, Index 1, Clocking Mode Register (RW; 0x3C4=1; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- 8/9 dot clocks
 ;           Eight dots (1) or Nine Clocks (0)
 ;
 ;      1 -- Reserved
 ;
 ;      2 -- Shift Load
 ;           If bit 4 is 0:
 ;           Reload serializers each char clock (0) or on every other (1)
 ;
 ;      3 -- Dot clock
 ;           Normal clock (0) or divide clock by 2 (1)
 ;
 ;      4 -- Shift 4
 ;           Reload serializers each char clock (0) or on each fourth (1)
 ;
 ;      5 -- Screen off
 ;           Video screen off and max mem bandwidth to CPU (1) or Normal operation (0)
 ;
 ;    6-7 -- Reserved
 ;;
  db 00000000b       ;0x00










;Sequencer Register, Index 2, Map Mask Register (RW; 0x3C4=2; 0x3C5):
;;
 ;
 ;  Bits:
 ;    0-3 -- Map mask
 ;           Enable (1) or disable writes (0) to the corresponding map, 0-3, with bits 0-3
 ;
 ;    All other bits are reserved.
 ;;
  db 00000011b       ;0x03










;Sequencer Register, Index 3, Character Map Select Register (RW; 0x3C4=3; 0x3C5):
;;
 ;
 ;  Bits:
 ;    4,1,0 -- Character Map Select B
 ;             000
 ;             1st 8K of Map 2
 ;
 ;    5,3,2 -- Character Map Select A
 ;             000
 ;             1st 8K of Map 2
 ;             NOTE: The value of Character Map Select A == Character Map Select B,
 ;                   so we will ignore Character Map Select A and use
 ;                   Character Map Select B configuration.
 ;
 ;    All other bits are reserved.
 ;;
  db 00000000b       ;0x00










;Sequencer Register, Index 4, Memory Mode Register (RW; 0x3C4=4; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Reserved
 ;
 ;      1 -- Extended Memory (1)
 ;           0 -- No extended memory present (less than 64K)
 ;           1 -- Extended memory present (more than 64K; use 256K;
 ;                also enables the Character Map Select feature)
 ;
 ;      2 -- Odd/Even (1)
 ;           0 -- Direct even addresses to maps 0 and 2 and odd addresses
 ;                to maps 1 and 3.
 ;           1 -- If bit 3 is 0: make the CPU access data sequentially
 ;                within a bit map.
 ;
 ;      3 -- Chain-4 (1)
 ;           0 -- If bit 2 is 1, make the CPU access data sequentially within
 ;                a bit map by the Map Mask Register.
 ;           1 -- Make the two lower address bits to select the map that will
 ;                be accessed.
 ;
 ;
 ;    4-7 -- Reserved
 ;;
;  db 00000010b       ;0x02
;db 7   ;in text mode causes planes to be badly selected and all
        ;letters have a different color.
db 2



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EGA_Text_80x25x16CRTCRegs:
;CRTC Controller, Index 0, Horizontal Total (RW; 0x3D4=0 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of horizontal characters MINUS 5
 ;;
;  db 95              ;0x5F
db 0x5F


;from 0x5F to 61h??????






;CRTC Controller, Index 1, Horizontal Display-Enable End (RW; 0x3D4=1 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
;  db 79              ;0x4F
db 0x4F

;from 4fh???? to 50h?????







;CRTC Controller, Index 2, Start Horizontal Blanking Register (RW; 0x3D4=2 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
;  db 01010000b       ;0x50
db 0x50









;CRTC Controller, Index 3, End Horizontal Blanking Register (RW; 0x3D4=3 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Blanking (2 here)
 ;
 ;      5,6 -- Display Enable Skew Control (0 here)
 ;
 ;        7 -- Test bit; must be 1
 ;;
;  db 10000010b       ;0x82
db 0x82









;CRTC Controller, Index 4, Start Horizontal Retrace Pulse (RW; 0x3D4=4 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Start Horizontal Retrace Pulse (84 here)
 ;;
;  db 01010101b       ;0x55
;db 0x55
db 0x54
;From 47h to 5h???







;CRTC Controller, Index 5, End Horizontal Retrace Pulse (RW; 0x3D4=5 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Retrace
 ;      5-6 -- Horizontal Retrace Delay
 ;        7 -- End Horizontal Blanking, Bit 5
 ;;
;  db 10000001b       ;0x81
;db 0x81
db 0x80








;CRTC Controller, Index 6, Vertical Total (RW; 0x3D4=6 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- 8 lower bits of number of horizontal raster scans MINUS 2
 ;;
;  db 10111111b       ;0xBF
db 0xBF









;CRTC Controller, Index 7, Overflow (RW; 0x3D4=7 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- bit 8 of vertical total, reg idx 0x06
 ;      1 -- bit 8 of vertical total, reg idx 0x12
 ;      2 -- bit 8 of vertical total, reg idx 0x10
 ;      3 -- bit 8 of vertical total, reg idx 0x15
 ;      4 -- bit 8 of vertical total, reg idx 0x18
 ;      5 -- bit 9 of vertical total, reg idx 0x06
 ;      6 -- bit 9 of vertical total, reg idx 0x12
 ;      7 -- bit 9 of vertical total, reg idx 0x10
 ;;
;  db 00011111b       ;0x1F
db 0x1F









;CRTC Controller, Index 8, Preset Row Scan (RW; 0x3D4=8 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- preset row scan
 ;      5-6 -- byte panning control
 ;      7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 9, Maximum Scan Line (RW; 0x3D4=9 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- maximum scan line
 ;        5 -- start vertical blank
 ;        6 -- line compare
 ;        7 -- 200 to 400 line conversion
 ;;
;  db 01001111b       ;0x4F
;db 0xC7
db 0x4F

;NOTE: This can duplicate the size of the font,
;      and the maximum scan line field could be
;      useful for instance for 8x8 modes and to be
;      able to use up to 32-line-height fonts, thus
;      the bit range 0-4, for 00000b (0) to 11111b (31).






;CRTC Controller, Index 10, Cursor Start (RW; 0x3D4=0x0A color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor start
 ;        5 -- cursor off
 ;      6-7 -- reserved
 ;;
;  db 00001110b       ;0x0E
;db 6
;db 0xD
db 0xE







;CRTC Controller, Index 11, Cursor End (RW; 0x3D4=0x0B color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor end
 ;      5-6 -- cursor skew
 ;        7 -- reserved
 ;;
;  db 00001111b       ;0x0F
;db 7
;db 0xE
db 0xF








;CRTC Controller, Index 12, Start Address High (RW; 0x3D4=0x0C color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address high
 ;;
  db 00000000b       ;0x00







;seems to affect horizontally, but has to do with vertical retrace



;CRTC Controller, Index 13, Start Address Low (RW; 0x3D4=0x0D color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address low
 ;;
  db 00000000b       ;0x00


;seems to affect horizontally, but has to do with vertical retrace







;CRTC Controller, Index 14, Cursor Location High (RW; 0x3D4=0x0E color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 15, Cursor Location Low (RW; 0x3D4=0x0F color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor low
 ;;
  db 00000000b       ;0x00









;CRTC Controller, Index 16, Vertical Retrace Start (W; 0x3D4=0x10 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 - lower 8 bits of vertical retrace pulse start position
 ;;
;  db 156             ;0x9C
db 0x9C


;From???? 0x90?? to 0xBF?






;CRTC Controller, Index 17, Vertical Retrace End (W; 0x3D4=0x11 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- vertical retrace end
 ;        4 -- clear vertical interrupt
 ;        5 -- enable vertical interrupt
 ;        6 -- select 5 refresh cycles
 ;        7 -- protect registers 0 to 7: True (1) or False (0)
 ;;
;  db 00001110b       ;0x0E
db 0x0E


;affects visually more the upper line of the screen (bits 0-3)






;CRTC Controller, Index 18, Vertical Display Enable End (RW; 0x3D4=0x12 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- vertical display enable end
 ;;
;  db 143             ;0x8F
db 0x8F

;from 8fh?? or even 0, to ffh (c0h is funny) -- see below.

;lower 8 bits of 10 bits that indicate the number of lines to show
;vertically before showing nothing.
;Bits 8 and 9 are in the overflow register bits 1 and 6 respectively,
;so here we have an overal value of 399 (as in 400 for 640x400 mode :) ).
;
;FROM HERE WE ARE FIRST STARTING TO UNDERSTAND HOW TO CONTROL
;SOME ASPECTS OF RESOLUTION AND OF SHOWING IT.
;
;And if we try to show more lines than existing, for instance
;FFh here for 80x25 text mode, the screen could scroll with a
;bad aspect.....







;CRTC Controller, Index 19, Offset (RW; 0x3D4=0x13 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- offset
 ;;
;  db 40              ;0x28
db 0x28









;CRTC Controller, Index 20, Underline Location (RW; 0x3D4=0x14 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- underline location
 ;        5 -- count by 4
 ;        6 -- double word mode
 ;        7 -- reserved
 ;;
;  db 00011111b       ;0x1F
db 0x1F


;NOTE: bits 0-4 could be associated with the maximum scan line field
;      in other register (I changed this alone, to 0, and didn't seem
;      to have any visual effect).

;      Bit 5 used alone (count by 4) is very interesting in text mode.
;      When enabled, it causes every character cell to be repeated
;      4 times (except the first character leftmost, repeated 3 times).
;      It also repeats the cursor, in 3 or 4 consecutive character cells.
;
;      Bit 6, double word mode, seems to use 4 bytes for a single
;      character in screen, and it also alters its display, in text mode,
;      to an almost unintelligible form, and also seems to duplicate
;      some content in the screen in 2 halves.




;CRTC Controller, Index 21, Start Vertical Blanking (RW; 0x3D4=0x15 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start vertical blank -- lower 8 bits of 10-bit register
 ;;
;  db 150             ;0x96
db 0x96


;NOTE: This field accepted 0 without trouble, without
;taking bits 8 and 9 in the overflow reg.
;
;Just caused a hole in some text lines past half the screen.






;CRTC Controller, Index 22, End Vertical Blanking (RW; 0x3D4=0x16 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- end vertical blank
 ;;
;  db 185             ;0xB9
db 0xB9









;CRTC Controller, Index 23, CRTC Mode Control (RW; 0x3D4=0x17 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- compatibility mode support
 ;      1 -- select row scan counter
 ;      2 -- horizontal retrace select
 ;      3 -- count by two
 ;      4 -- reserved
 ;      5 -- address wrap
 ;      6 -- word mode (0) or byte mode (1)
 ;      7 -- hardware reset
 ;;
;  db 10100011b       ;0xA3
db 0xA3

;This is another interesting register,
;specially bit 6 and bit 3, the most visual ones.

;The count by 2 field is like the count by 4, only that
;a character is shown 2 times consecutively instead of 4.
;The leftmost screen characters are only shown once.

;NOTE: This count by 2 bit has precedence over the count by 4
;      bit in other register. If count by 2 is enabled,
;      then count by 4 has no visual effect.






;CRTC Controller, Index 24, Line Compare (RW; 0x3D4=0x18 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- lower 8 bits of compare target.
 ;             Bit 8 is in Overflow register index 7.
 ;             Bit 9 is in Maximum Scan Line register index 9. 
 ;;
  db 11111111b       ;0xFF


;NOTE: Changing this very register to 0 didn't seem to have any effect.


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EGA_Text_80x25x16GraphicsRegs:
;Graphics Controller Register, Index 0, Set/Reset (RW; 0x3CE=0; 0x3CF):
;;
 ;
 ;  Bits:
 ;      0-3 -- Set/Reset
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 1, Enable Set/Reset (RW; 0x3CE=1; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Enable Set/Reset
 ;             1 -- If write mode is 0, and the bit for the map is 1 here,
 ;                  write memory address with the value of the Set/Reset register.
 ;
 ;             0 -- If write mode is 0, and the bit for the map is 0 here,
 ;                  write memory address with the value of system CPU.
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 2, Color Compare (RW; 0x3CE=2; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Color compare
 ;             Color Compare Map n, where n is the bit position
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 3, Data Rotate (RW; 0x3CE=3; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-2 -- Data rotate
 ;             Number of bits to right-rotate CPU data (0 here)
 ;
 ;      3,4 -- Function select
 ;             00 -- unmodified   <-- this one!!!!!!
 ;             01 -- AND data with latch
 ;             10 -- OR data with latch
 ;             11 -- XOR data with latch
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x0










;Graphics Controller Register, Index 4, Read Map Select (RW; 0x3CE=4; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Read Map Select
 ;             Select maps 0 to 3 for system read operations (map 0 here)
 ;
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 5, Graphics Mode (RW; 0x3CE=5; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Write Mode
 ;             Select write mode 0 to 3 (0 here)
 ;
 ;        2 -- Reserved, undefined on read
 ;
 ;        3 -- Read Type
 ;
 ;        4 -- Odd/Even
 ;
 ;        5 -- Shift Register
 ;
 ;        6 -- 256 Color Mode
 ;
 ;        7 -- Reserved
 ;;
;  db 00010000b       ;0x10
db 0x10










;Graphics Controller Register, Index 6, Miscellaneous (RW; 0x3CE=6; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;        0 -- Graphics Mode
 ;             Graphics Mode (1) or Text Mode (0)
 ;
 ;        1 -- Odd/Even
 ;
 ;      2,3 -- Memory Map (3 here)
 ;                    Map 0 -- 0xA0000-0xBFFFF
 ;                    Map 1 -- 0xA0000-0xAFFFF
 ;                    Map 2 -- 0xB0000-0xBFFFF
 ;                    Map 3 -- 0xB8000-0xBFFFF
 ;
 ;      4-7 -- Reserved
 ;;
;  db 00001110b       ;0x0E
db 0x0E









;Graphics Controller Register, Index 7, Color Don't Care (RW; 0x3CE=7; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- For each bit, if 0, don't participate in color
 ;             compare cycle; if 1 participate in it for that map.
 ;;
;  db 00000000b       ;0x00


db 0x00







;Graphics Controller Register, Index 8, Bit Mask (RW; 0x3CE=8; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Bit mask
 ;;
;  db 11111111b       ;0xFF

db 0xFF


;DONE

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EGA_Text_80x25x16AttributeRegs:
;Attribute Controller Register, Index 0, Palette 0 (RW; 0x3C0=0; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 0               ;0x00










;Attribute Controller Register, Index 1, Palette 1 (RW; 0x3C0=1; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 1               ;0x01










;Attribute Controller Register, Index 2, Palette 2 (RW; 0x3C0=2; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 2               ;0x02










;Attribute Controller Register, Index 3, Palette 3 (RW; 0x3C0=3; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 3               ;0x03










;Attribute Controller Register, Index 4, Palette 4 (RW; 0x3C0=4; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 4               ;0x04










;Attribute Controller Register, Index 5, Palette 5 (RW; 0x3C0=5; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 5               ;0x05










;Attribute Controller Register, Index 6, Palette 6 (RW; 0x3C0=6; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 20              ;0x14










;Attribute Controller Register, Index 7, Palette 7 (RW; 0x3C0=7; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 7               ;0x07










;Attribute Controller Register, Index 8, Palette 8 (RW; 0x3C0=8; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 56              ;0x38










;Attribute Controller Register, Index 9, Palette 9 (RW; 0x3C0=9; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 57              ;0x39










;Attribute Controller Register, Index 10, Palette 10 (RW; 0x3C0=0x0A; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 58              ;0x3A










;Attribute Controller Register, Index 11, Palette 11 (RW; 0x3C0=0x0B; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 59              ;0x3B










;Attribute Controller Register, Index 12, Palette 12 (RW; 0x3C0=0x0C; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 60              ;0x3C










;Attribute Controller Register, Index 13, Palette 13 (RW; 0x3C0=0x0D; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 61              ;0x3D










;Attribute Controller Register, Index 14, Palette 14 (RW; 0x3C0=0x0E; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 62              ;0x3E










;Attribute Controller Register, Index 15, Palette 15 (RW; 0x3C0=0x0F; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 63              ;0x3F










;Attribute Controller, Index 16, Attribute Mode Control (RW; 0x3C0=0x10; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- graphics/alphanumeric
 ;      1 -- mono emulation
 ;      2 -- enable line graphics character codes
 ;      3 -- enable blink/select background intensity
 ;      4 -- reserved
 ;      5 -- PEL panning compatibility
 ;      6 -- PEL width
 ;      7 -- P5, P4 select
 ;
 ;;
  db 00001100b       ;0x0C










;Attribute Controller, Index 17, Overscan Color (RW; 0x3C0=0x11; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- overscan color
 ;
 ;;
  db 00000000b       ;0x00 or black



;If we disable the palette, everything seems to turn into
;the overscan color, if it isn't black.

;IMPORTANT NOTE: The Attribute controller expects
;                to first write the index and then the value
;                or to write those 2 bytes with a word IO instruction.
;                Otherwise, it behaves as a flip-flop.
;
;                Probably, or probably not, the other controllers
;                behave like this, so let's find that out too.





;Attribute Controller, Index 18, Color Plane Enable (RW; 0x3C0=0x12; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- enable color plane
 ;      4-5 -- video status MUX
 ;      6-7 -- reserved
 ;
 ;;
  db 00001111b       ;0x0F










;Attribute Controller, Index 19, Horizontal PEL Panning (RW; 0x3C0=0x13; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- horizontal PEL panning
 ;      4-7 -- reserved
 ;
 ;;
;  db 00000100b       ;0x08      <---- very interesting error'
;  db 00001000b       ;0x08
;db 0
db 8



;'If we use a loop to slowly change this value increasingly/decreasingly,
; we can learn something.
;
; The effect of using 4 instead of 8 was that the screen was "wrapped",
; and some pixels at the leftmost of the screen were shown at the rightmost
; of the screen........





;Attribute Controller, Index 20, Color Select (RW; 0x3C0=0x14; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- SC5,SC4
 ;      2-3 -- SC6,SC7
 ;      4-7 -- Reserved
 ;
 ;;
  db 00000000b       ;0x00


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Register Values for Mode 3h (256-color palette)

Post by ~ »

Palette, Mode 3h, Text, 80x25x16 Colors, EGA

It's a 16-color mode, so the palette indexes into the 256-color palette are integrated into 16 color registers in the main VGA register set. Also, only the first 16 colors are used.

It looks like all standard 4-color and 16-color CGA/EGA/VGA modes use the exact same default palette from the BIOS, so in the final code we will only include a single palette for that called PALETTE256_4_16_colors.

Howevever, every color index can select between 64 different colors, but there are just 16 colors selected at a time on screen.

The palette below contains 64 different colors.

Code: Select all

;Version 2013-03-10
;;

PALETTE_80x25x16:
  PALETTE_80x25x16_Color_0: db 0x0,0x0,0x0
  PALETTE_80x25x16_Color_1: db 0x0,0x0,0x2A
  PALETTE_80x25x16_Color_2: db 0x0,0x2A,0x0
  PALETTE_80x25x16_Color_3: db 0x0,0x2A,0x2A
  PALETTE_80x25x16_Color_4: db 0x2A,0x0,0x0
  PALETTE_80x25x16_Color_5: db 0x2A,0x0,0x2A
  PALETTE_80x25x16_Color_6: db 0x2A,0x2A,0x0
  PALETTE_80x25x16_Color_7: db 0x2A,0x2A,0x2A
  PALETTE_80x25x16_Color_8: db 0x0,0x0,0x15
  PALETTE_80x25x16_Color_9: db 0x0,0x0,0x3F
  PALETTE_80x25x16_Color_10: db 0x0,0x2A,0x15
  PALETTE_80x25x16_Color_11: db 0x0,0x2A,0x3F
  PALETTE_80x25x16_Color_12: db 0x2A,0x0,0x15
  PALETTE_80x25x16_Color_13: db 0x2A,0x0,0x3F
  PALETTE_80x25x16_Color_14: db 0x2A,0x2A,0x15
  PALETTE_80x25x16_Color_15: db 0x2A,0x2A,0x3F
  PALETTE_80x25x16_Color_16: db 0x0,0x15,0x0
  PALETTE_80x25x16_Color_17: db 0x0,0x15,0x2A
  PALETTE_80x25x16_Color_18: db 0x0,0x3F,0x0
  PALETTE_80x25x16_Color_19: db 0x0,0x3F,0x2A
  PALETTE_80x25x16_Color_20: db 0x2A,0x15,0x0
  PALETTE_80x25x16_Color_21: db 0x2A,0x15,0x2A
  PALETTE_80x25x16_Color_22: db 0x2A,0x3F,0x0
  PALETTE_80x25x16_Color_23: db 0x2A,0x3F,0x2A
  PALETTE_80x25x16_Color_24: db 0x0,0x15,0x15
  PALETTE_80x25x16_Color_25: db 0x0,0x15,0x3F
  PALETTE_80x25x16_Color_26: db 0x0,0x3F,0x15
  PALETTE_80x25x16_Color_27: db 0x0,0x3F,0x3F
  PALETTE_80x25x16_Color_28: db 0x2A,0x15,0x15
  PALETTE_80x25x16_Color_29: db 0x2A,0x15,0x3F
  PALETTE_80x25x16_Color_30: db 0x2A,0x3F,0x15
  PALETTE_80x25x16_Color_31: db 0x2A,0x3F,0x3F
  PALETTE_80x25x16_Color_32: db 0x15,0x0,0x0
  PALETTE_80x25x16_Color_33: db 0x15,0x0,0x2A
  PALETTE_80x25x16_Color_34: db 0x15,0x2A,0x0
  PALETTE_80x25x16_Color_35: db 0x15,0x2A,0x2A
  PALETTE_80x25x16_Color_36: db 0x3F,0x0,0x0
  PALETTE_80x25x16_Color_37: db 0x3F,0x0,0x2A
  PALETTE_80x25x16_Color_38: db 0x3F,0x2A,0x0
  PALETTE_80x25x16_Color_39: db 0x3F,0x2A,0x2A
  PALETTE_80x25x16_Color_40: db 0x15,0x0,0x15
  PALETTE_80x25x16_Color_41: db 0x15,0x0,0x3F
  PALETTE_80x25x16_Color_42: db 0x15,0x2A,0x15
  PALETTE_80x25x16_Color_43: db 0x15,0x2A,0x3F
  PALETTE_80x25x16_Color_44: db 0x3F,0x0,0x15
  PALETTE_80x25x16_Color_45: db 0x3F,0x0,0x3F
  PALETTE_80x25x16_Color_46: db 0x3F,0x2A,0x15
  PALETTE_80x25x16_Color_47: db 0x3F,0x2A,0x3F
  PALETTE_80x25x16_Color_48: db 0x15,0x15,0x0
  PALETTE_80x25x16_Color_49: db 0x15,0x15,0x2A
  PALETTE_80x25x16_Color_50: db 0x15,0x3F,0x0
  PALETTE_80x25x16_Color_51: db 0x15,0x3F,0x2A
  PALETTE_80x25x16_Color_52: db 0x3F,0x15,0x0
  PALETTE_80x25x16_Color_53: db 0x3F,0x15,0x2A
  PALETTE_80x25x16_Color_54: db 0x3F,0x3F,0x0
  PALETTE_80x25x16_Color_55: db 0x3F,0x3F,0x2A
  PALETTE_80x25x16_Color_56: db 0x15,0x15,0x15
  PALETTE_80x25x16_Color_57: db 0x15,0x15,0x3F
  PALETTE_80x25x16_Color_58: db 0x15,0x3F,0x15
  PALETTE_80x25x16_Color_59: db 0x15,0x3F,0x3F
  PALETTE_80x25x16_Color_60: db 0x3F,0x15,0x15
  PALETTE_80x25x16_Color_61: db 0x3F,0x15,0x3F
  PALETTE_80x25x16_Color_62: db 0x3F,0x3F,0x15
  PALETTE_80x25x16_Color_63: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_64: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_65: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_66: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_67: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_68: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_69: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_70: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_71: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_72: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_73: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_74: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_75: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_76: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_77: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_78: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_79: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_80: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_81: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_82: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_83: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_84: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_85: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_86: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_87: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_88: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_89: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_90: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_91: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_92: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_93: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_94: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_95: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_96: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_97: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_98: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_99: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_100: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_101: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_102: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_103: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_104: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_105: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_106: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_107: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_108: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_109: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_110: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_111: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_112: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_113: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_114: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_115: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_116: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_117: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_118: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_119: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_120: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_121: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_122: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_123: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_124: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_125: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_126: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_127: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_128: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_129: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_130: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_131: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_132: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_133: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_134: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_135: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_136: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_137: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_138: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_139: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_140: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_141: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_142: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_143: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_144: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_145: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_146: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_147: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_148: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_149: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_150: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_151: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_152: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_153: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_154: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_155: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_156: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_157: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_158: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_159: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_160: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_161: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_162: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_163: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_164: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_165: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_166: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_167: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_168: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_169: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_170: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_171: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_172: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_173: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_174: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_175: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_176: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_177: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_178: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_179: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_180: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_181: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_182: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_183: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_184: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_185: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_186: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_187: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_188: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_189: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_190: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_191: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_192: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_193: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_194: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_195: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_196: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_197: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_198: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_199: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_200: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_201: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_202: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_203: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_204: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_205: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_206: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_207: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_208: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_209: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_210: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_211: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_212: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_213: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_214: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_215: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_216: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_217: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_218: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_219: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_220: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_221: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_222: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_223: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_224: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_225: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_226: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_227: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_228: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_229: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_230: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_231: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_232: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_233: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_234: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_235: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_236: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_237: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_238: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_239: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_240: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_241: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_242: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_243: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_244: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_245: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_246: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_247: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_248: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_249: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_250: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_251: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_252: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_253: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_254: db 0x3F,0x3F,0x3F
  PALETTE_80x25x16_Color_255: db 0x3F,0x3F,0x3F


Last edited by ~ on Tue May 24, 2016 3:01 pm, edited 2 times in total.
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Register Values for Mode 3h (Default text font)

Post by ~ »

Default Text Font, Mode 3h, Text, 80x25x16 Colors, EGA

Please see the following link and the attachment (demonstration of the format for the first 11 ASCII characters below):
8x16_default_font.asm


Code: Select all

;Version 2013-03-10
;;

VGA_Hardware_Font_8x16_default:

;Character #0
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #1
;;
;;;
db 00000000b
db 00000000b
db 01111110b
db 10000001b
db 10100101b
db 10000001b
db 10000001b
db 10111101b
db 10011001b
db 10000001b
db 10000001b
db 01111110b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #2
;;
;;;
db 00000000b
db 00000000b
db 01111110b
db 11111111b
db 11011011b
db 11111111b
db 11111111b
db 11000011b
db 11100111b
db 11111111b
db 11111111b
db 01111110b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #3
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 01101100b
db 11111110b
db 11111110b
db 11111110b
db 11111110b
db 01111100b
db 00111000b
db 00010000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #4
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00010000b
db 00111000b
db 01111100b
db 11111110b
db 01111100b
db 00111000b
db 00010000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #5
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00011000b
db 00111100b
db 00111100b
db 11100111b
db 11100111b
db 11100111b
db 00011000b
db 00011000b
db 00111100b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #6
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00011000b
db 00111100b
db 01111110b
db 11111111b
db 11111111b
db 01111110b
db 00011000b
db 00011000b
db 00111100b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #7
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00011000b
db 00111100b
db 00111100b
db 00011000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #8
;;
;;;
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11100111b
db 11000011b
db 11000011b
db 11100111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b




;Character #9
;;
;;;
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00111100b
db 01100110b
db 01000010b
db 01000010b
db 01100110b
db 00111100b
db 00000000b
db 00000000b
db 00000000b
db 00000000b
db 00000000b




;Character #10
;;
;;;
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11000011b
db 10011001b
db 10111101b
db 10111101b
db 10011001b
db 11000011b
db 11111111b
db 11111111b
db 11111111b
db 11111111b
db 11111111b


Attachments
8x16_default_font.asm.zip
(3.67 KiB) Downloaded 30 times
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Register Values for Mode 4h (Registers)

Post by ~ »

Register Values, Mode 4h, Graphics, 320x200x4 Colors, CGA

Code: Select all

;Version 2013-06-24
;;

CGA_320x200x4Gen__MiscOutputReg:
;General Register, Miscellaneous Output (W; 0x3C2):
;;
 ;
 ;  Bits:
 ;      0 -- I/O Address select
 ;           Color Emulation  (1) or Monochrome Emulation   (0)
 ;
 ;      1 -- Enable RAM
 ;           Enable video RAM (1) or Disable address decode (0)
 ;
 ;    2,3 -- Clock Select - ??? - I currently don't know where is the CS2 bit
 ;                                so I don't know what configuration is selected here
 ;           CS2  CS1  CS0  Clock
 ;           ---  ---  ---  -----
 ;            0    0    0   25.175 MHz    ;<--this one!!!!!!!
 ;            0    0    1   28.322 MHz
 ;         -------------------------------Below this line, consider Oak-specific values
 ;            0    1    0   65 MHz (external clock per true VGA standard)
 ;            0    1    1   44.9 MHz (undefined per true VGA standard)
 ;            1    0    0   14.161 MHz (derived from 28.322 MHz)
 ;            1    0    1   18 MHz (derived from 36 MHz)
 ;            1    1    0   40 MHz
 ;            1    1    1   36 MHz
 ;
 ;      4 -- Reserved
 ;            (0)
 ;
 ;      5 -- Page bit for odd/even
 ;           High 64K         (1) or Low 64K                (0) page of memory
 ;
 ;      6 -- Horizontal Sync Polarity
 ;           Negative         (1) or Posite Vertic. Retrace (0)
 ;
 ;      7 -- Vertical Sync Polarity
 ;           Positive         (0) or Negative Vert. Retrace (0)
 ;
 ;      Bits 7-6
 ;      --------
 ;            00 -- reserved
 ;            01 -- 400 lines     ;<-- This one!
 ;            10 -- 350 lines
 ;            11 -- 480 lines
 ;
 ;
 ;
 ;
 ;
 ;;
  db 01100011b       ;0x63










CGA_320x200x4Gen__FeatureControlReg:
;General Register, Feature Control (RW; 0x3DA color; 0x3BA mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      3 -- Vertical Sync Select
 ;           Normal (0) or Logical OR of Vertical Sync End/Vertical Display Enable (1)
 ;
 ;      All other bits are Reserved
 ;
 ;;
  db 00000000b       ;0x00




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CGA_320x200x4Gen__SequencerRegs:
;Sequencer Register, Index 0, Reset Register (RW; 0x3C4=0; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Asynchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      1 -- Synchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      All other bits are reserved
 ;;
  db 00000011b       ;0x03










;Sequencer Register, Index 1, Clocking Mode Register (RW; 0x3C4=1; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- 8/9 dot clocks
 ;           Eight dots (1) or Nine Clocks (0)
 ;
 ;      1 -- Reserved
 ;
 ;      2 -- Shift Load
 ;           If bit 4 is 0:
 ;           Reload serializers each char clock (0) or on every other (1)
 ;
 ;      3 -- Dot clock
 ;           Normal clock (0) or divide clock by 2 (1)
 ;
 ;      4 -- Shift 4
 ;           Reload serializers each char clock (0) or on each fourth (1)
 ;
 ;      5 -- Screen off
 ;           Video screen off and max mem bandwidth to CPU (1) or Normal operation (0)
 ;
 ;    6-7 -- Reserved
 ;;
  db 00001001b       ;0x09










;Sequencer Register, Index 2, Map Mask Register (RW; 0x3C4=2; 0x3C5):
;;
 ;
 ;  Bits:
 ;    0-3 -- Map mask
 ;           Enable (1) or disable writes (0) to the corresponding map, 0-3, with bits 0-3
 ;
 ;    All other bits are reserved.
 ;;
  db 00000011b       ;0x0F










;Sequencer Register, Index 3, Character Map Select Register (RW; 0x3C4=3; 0x3C5):
;;
 ;
 ;  Bits:
 ;    4,1,0 -- Character Map Select B
 ;             000
 ;             1st 8K of Map 2
 ;
 ;    5,3,2 -- Character Map Select A
 ;             000
 ;             1st 8K of Map 2
 ;             NOTE: The value of Character Map Select A == Character Map Select B,
 ;                   so we will ignore Character Map Select A and use
 ;                   Character Map Select B configuration.
 ;
 ;    All other bits are reserved.
 ;;
  db 00000000b       ;0x00










;Sequencer Register, Index 4, Memory Mode Register (RW; 0x3C4=4; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Reserved
 ;
 ;      1 -- Extended Memory (1)
 ;           0 -- No extended memory present (less than 64K)
 ;           1 -- Extended memory present (more than 64K; use 256K;
 ;                also enables the Character Map Select feature)
 ;
 ;      2 -- Odd/Even (1)
 ;           0 -- Direct even addresses to maps 0 and 2 and odd addresses
 ;                to maps 1 and 3.
 ;           1 -- If bit 3 is 0: make the CPU access data sequentially
 ;                within a bit map.
 ;
 ;      3 -- Chain-4 (1)
 ;           0 -- If bit 2 is 1, make the CPU access data sequentially within
 ;                a bit map by the Map Mask Register.
 ;           1 -- Make the two lower address bits to select the map that will
 ;                be accessed.
 ;
 ;
 ;    4-7 -- Reserved
 ;;
  db 00000010b       ;0x0E




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CGA_320x200x4Gen__CRTCRegs:
;CRTC Controller, Index 0, Horizontal Total (RW; 0x3D4=0 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of horizontal characters MINUS 5
 ;;
  db 45              ;0x2D










;CRTC Controller, Index 1, Horizontal Display-Enable End (RW; 0x3D4=1 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 39              ;0x27










;CRTC Controller, Index 2, Start Horizontal Blanking Register (RW; 0x3D4=2 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 40        ;0x28










;CRTC Controller, Index 3, End Horizontal Blanking Register (RW; 0x3D4=3 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Blanking (16 here)
 ;
 ;      5,6 -- Display Enable Skew Control (0 here)
 ;
 ;        7 -- Test bit; must be 1
 ;;
  db 10010000b       ;0x90










;CRTC Controller, Index 4, Start Horizontal Retrace Pulse (RW; 0x3D4=4 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Start Horizontal Retrace Pulse (43 here)
 ;;
  db 43       ;0x2B










;CRTC Controller, Index 5, End Horizontal Retrace Pulse (RW; 0x3D4=5 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Retrace
 ;      5-6 -- Horizontal Retrace Delay
 ;        7 -- End Horizontal Blanking, Bit 5
 ;;
  db 10000000b       ;0x80










;CRTC Controller, Index 6, Vertical Total (RW; 0x3D4=6 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- 8 lower bits of number of horizontal raster scans MINUS 2
 ;;
  db 10111111b       ;0xBF










;CRTC Controller, Index 7, Overflow (RW; 0x3D4=7 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- bit 8 of vertical total, reg idx 0x06
 ;      1 -- bit 8 of vertical total, reg idx 0x12
 ;      2 -- bit 8 of vertical total, reg idx 0x10
 ;      3 -- bit 8 of vertical total, reg idx 0x15
 ;      4 -- bit 8 of vertical total, reg idx 0x18
 ;      5 -- bit 9 of vertical total, reg idx 0x06
 ;      6 -- bit 9 of vertical total, reg idx 0x12
 ;      7 -- bit 9 of vertical total, reg idx 0x10
 ;;
  db 00011111b       ;0x1F










;CRTC Controller, Index 8, Preset Row Scan (RW; 0x3D4=8 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- preset row scan
 ;      5-6 -- byte panning control
 ;      7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 9, Maximum Scan Line (RW; 0x3D4=9 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- maximum scan line
 ;        5 -- start vertical blank
 ;        6 -- line compare
 ;        7 -- 200 to 400 line conversion
 ;;
  db 01000001b       ;0x41










;CRTC Controller, Index 10, Cursor Start (RW; 0x3D4=0x0A color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor start
 ;        5 -- cursor off
 ;      6-7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 11, Cursor End (RW; 0x3D4=0x0B color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor end
 ;      5-6 -- cursor skew
 ;        7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 12, Start Address High (RW; 0x3D4=0x0C color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 13, Start Address Low (RW; 0x3D4=0x0D color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address low
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 14, Cursor Location High (RW; 0x3D4=0x0E color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 15, Cursor Location Low (RW; 0x3D4=0x0F color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor low
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 16, Vertical Retrace Start (W; 0x3D4=0x10 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 - lower 8 bits of vertical retrace pulse start position
 ;;
  db 156             ;0x9C










;CRTC Controller, Index 17, Vertical Retrace End (W; 0x3D4=0x11 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- vertical retrace end
 ;        4 -- clear vertical interrupt
 ;        5 -- enable vertical interrupt
 ;        6 -- select 5 refresh cycles
 ;        7 -- protect registers 0 to 7 enabled (0) or disabled (1)
 ;;
  db 00001110b       ;0x0E










;CRTC Controller, Index 18, Vertical Display Enable End (RW; 0x3D4=0x12 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- vertical display enable end
 ;;
  db 143             ;0x8F










;CRTC Controller, Index 19, Offset (RW; 0x3D4=0x13 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- offset
 ;;
  db 20              ;0x14










;CRTC Controller, Index 20, Underline Location (RW; 0x3D4=0x14 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- underline location
 ;        5 -- count by 4
 ;        6 -- double word mode
 ;        7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 21, Start Vertical Blanking (RW; 0x3D4=0x15 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start vertical blank -- lower 8 bits of 10-bit register
 ;;
  db 150             ;0x96










;CRTC Controller, Index 22, End Vertical Blanking (RW; 0x3D4=0x16 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- end vertical blank
 ;;
  db 185             ;0xB9










;CRTC Controller, Index 23, CRTC Mode Control (RW; 0x3D4=0x17 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- compatibility mode support
 ;      1 -- select row scan counter
 ;      2 -- horizontal retrace select
 ;      3 -- count by two
 ;      4 -- reserved
 ;      5 -- address wrap
 ;      6 -- word mode (0) or byte mode (1)
 ;      7 -- hardware reset
 ;;
  db 10100011b       ;0xA3










;CRTC Controller, Index 24, Line Compare (RW; 0x3D4=0x18 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- lower 8 bits of compare target.
 ;             Bit 8 is in Overflow register index 7.
 ;             Bit 9 is in Maximum Scan Line register index 9. 
 ;;
  db 11111111b       ;0xFF




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CGA_320x200x4Gen__GraphicsRegs:
;Graphics Controller Register, Index 0, Set/Reset (RW; 0x3CE=0; 0x3CF):
;;
 ;
 ;  Bits:
 ;      0-3 -- Set/Reset
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 1, Enable Set/Reset (RW; 0x3CE=1; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Enable Set/Reset
 ;             1 -- If write mode is 0, and the bit for the map is 1 here,
 ;                  write memory address with the value of the Set/Reset register.
 ;
 ;             0 -- If write mode is 0, and the bit for the map is 0 here,
 ;                  write memory address with the value of system CPU.
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 2, Color Compare (RW; 0x3CE=2; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Color compare
 ;             Color Compare Map n, where n is the bit position
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 3, Data Rotate (RW; 0x3CE=3; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-2 -- Data rotate
 ;             Number of bits to right-rotate CPU data (0 here)
 ;
 ;      3,4 -- Function select
 ;             00 -- unmodified   <-- this one!!!!!!
 ;             01 -- AND data with latch
 ;             10 -- OR data with latch
 ;             11 -- XOR data with latch
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x0










;Graphics Controller Register, Index 4, Read Map Select (RW; 0x3CE=4; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Read Map Select
 ;             Select maps 0 to 3 for system read operations (map 0 here)
 ;
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 5, Graphics Mode (RW; 0x3CE=5; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Write Mode
 ;             Select write mode 0 to 3 (0 here)
 ;
 ;        2 -- Reserved, undefined on read
 ;
 ;        3 -- Read Type
 ;
 ;        4 -- Odd/Even
 ;
 ;        5 -- Shift Register
 ;
 ;        6 -- 256 Color Mode
 ;
 ;        7 -- Reserved
 ;;
  db 00110000b       ;0x30










;Graphics Controller Register, Index 6, Miscellaneous (RW; 0x3CE=6; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;        0 -- Graphics Mode
 ;             Graphics Mode (1) or Text Mode (0)
 ;
 ;        1 -- Odd/Even
 ;
 ;      2,3 -- Memory Map (1 here)
 ;                    Map 0 -- 0xA0000-0xBFFFF
 ;                    Map 1 -- 0xA0000-0xAFFFF
 ;                    Map 2 -- 0xB0000-0xBFFFF
 ;                    Map 3 -- 0xB8000-0xBFFFF
 ;
 ;      4-7 -- Reserved
 ;;
  db 00000011b       ;0x03










;Graphics Controller Register, Index 7, Color Don't Care (RW; 0x3CE=7; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- For each bit, if 0, don't participate in color
 ;             compare cycle; if 1 participate in it for that map.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 8, Bit Mask (RW; 0x3CE=8; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Bit mask
 ;;
  db 11111111b       ;0xFF




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CGA_320x200x4Gen__AttributeRegs:
;Attribute Controller Register, Index 0, Palette 0 (RW; 0x3C0=0; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 0               ;0x00










;Attribute Controller Register, Index 1, Palette 1 (RW; 0x3C0=1; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 19              ;0x13










;Attribute Controller Register, Index 2, Palette 2 (RW; 0x3C0=2; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 21              ;0x15










;Attribute Controller Register, Index 3, Palette 3 (RW; 0x3C0=3; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 23              ;0x17










;Attribute Controller Register, Index 4, Palette 4 (RW; 0x3C0=4; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 2               ;0x02










;Attribute Controller Register, Index 5, Palette 5 (RW; 0x3C0=5; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 4               ;0x04










;Attribute Controller Register, Index 6, Palette 6 (RW; 0x3C0=6; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 6               ;0x06










;Attribute Controller Register, Index 7, Palette 7 (RW; 0x3C0=7; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 7               ;0x07










;Attribute Controller Register, Index 8, Palette 8 (RW; 0x3C0=8; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 16              ;0x10










;Attribute Controller Register, Index 9, Palette 9 (RW; 0x3C0=9; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 17              ;0x11










;Attribute Controller Register, Index 10, Palette 10 (RW; 0x3C0=0x0A; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 18              ;0x12










;Attribute Controller Register, Index 11, Palette 11 (RW; 0x3C0=0x0B; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 19              ;0x13










;Attribute Controller Register, Index 12, Palette 12 (RW; 0x3C0=0x0C; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 20              ;0x14










;Attribute Controller Register, Index 13, Palette 13 (RW; 0x3C0=0x0D; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 21              ;0x15










;Attribute Controller Register, Index 14, Palette 14 (RW; 0x3C0=0x0E; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 22              ;0x16










;Attribute Controller Register, Index 15, Palette 15 (RW; 0x3C0=0x0F; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 23              ;0x17










;Attribute Controller, Index 16, Attribute Mode Control (RW; 0x3C0=0x10; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- graphics/alphanumeric
 ;      1 -- mono emulation
 ;      2 -- enable line graphics character codes
 ;      3 -- enable blink/select background intensity
 ;      4 -- reserved
 ;      5 -- PEL panning compatibility
 ;      6 -- PEL width
 ;      7 -- P5, P4 select
 ;
 ;;
  db 00000001b       ;0x01










;Attribute Controller, Index 17, Overscan Color (RW; 0x3C0=0x11; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- overscan color
 ;
 ;;
  db 00000000b       ;0x00 or black










;Attribute Controller, Index 18, Color Plane Enable (RW; 0x3C0=0x12; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- enable color plane
 ;      4-5 -- video status MUX
 ;      6-7 -- reserved
 ;
 ;;
  db 00000011b       ;0x03










;Attribute Controller, Index 19, Horizontal PEL Panning (RW; 0x3C0=0x13; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- horizontal PEL panning
 ;      4-7 -- reserved
 ;
 ;;
  db 00000000b       ;0x00










;Attribute Controller, Index 20, Color Select (RW; 0x3C0=0x14; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- SC5,SC4
 ;      2-3 -- SC6,SC7
 ;      4-7 -- Reserved
 ;
 ;;
  db 00000000b       ;0x00


Last edited by ~ on Tue May 24, 2016 2:17 pm, edited 1 time in total.
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Register Values for Mode 4h (256-color palette)

Post by ~ »

Palette, Mode 4h, Graphics, 320x200x4 Colors, CGA

This one seems to be the same palette for Text Mode 80x25x16 Colors.

It's a 4-color mode, so the palette indexes into the 256-color palette are integrated into 4 color registers in the main VGA register set. Also, only the first 4 colors are used.

It looks like all standard 4-color and 16-color CGA/EGA/VGA modes use the exact same default palette from the BIOS, so in the final code we will only include a single palette for that called PALETTE256_4_16_colors.

Howevever, every color index can select between 64 different colors, but there are just 4 colors selected at a time on screen.

The palette below contains 64 different colors.

Code: Select all

;Version 2013-03-10
;;

PALETTE_320x200x4:
  PALETTE_320x200x4_Color_0: db 0x0,0x0,0x0
  PALETTE_320x200x4_Color_1: db 0x0,0x0,0x2A
  PALETTE_320x200x4_Color_2: db 0x0,0x2A,0x0
  PALETTE_320x200x4_Color_3: db 0x0,0x2A,0x2A
  PALETTE_320x200x4_Color_4: db 0x2A,0x0,0x0
  PALETTE_320x200x4_Color_5: db 0x2A,0x0,0x2A
  PALETTE_320x200x4_Color_6: db 0x2A,0x2A,0x0
  PALETTE_320x200x4_Color_7: db 0x2A,0x2A,0x2A
  PALETTE_320x200x4_Color_8: db 0x0,0x0,0x15
  PALETTE_320x200x4_Color_9: db 0x0,0x0,0x3F
  PALETTE_320x200x4_Color_10: db 0x0,0x2A,0x15
  PALETTE_320x200x4_Color_11: db 0x0,0x2A,0x3F
  PALETTE_320x200x4_Color_12: db 0x2A,0x0,0x15
  PALETTE_320x200x4_Color_13: db 0x2A,0x0,0x3F
  PALETTE_320x200x4_Color_14: db 0x2A,0x2A,0x15
  PALETTE_320x200x4_Color_15: db 0x2A,0x2A,0x3F
  PALETTE_320x200x4_Color_16: db 0x0,0x15,0x0
  PALETTE_320x200x4_Color_17: db 0x0,0x15,0x2A
  PALETTE_320x200x4_Color_18: db 0x0,0x3F,0x0
  PALETTE_320x200x4_Color_19: db 0x0,0x3F,0x2A
  PALETTE_320x200x4_Color_20: db 0x2A,0x15,0x0
  PALETTE_320x200x4_Color_21: db 0x2A,0x15,0x2A
  PALETTE_320x200x4_Color_22: db 0x2A,0x3F,0x0
  PALETTE_320x200x4_Color_23: db 0x2A,0x3F,0x2A
  PALETTE_320x200x4_Color_24: db 0x0,0x15,0x15
  PALETTE_320x200x4_Color_25: db 0x0,0x15,0x3F
  PALETTE_320x200x4_Color_26: db 0x0,0x3F,0x15
  PALETTE_320x200x4_Color_27: db 0x0,0x3F,0x3F
  PALETTE_320x200x4_Color_28: db 0x2A,0x15,0x15
  PALETTE_320x200x4_Color_29: db 0x2A,0x15,0x3F
  PALETTE_320x200x4_Color_30: db 0x2A,0x3F,0x15
  PALETTE_320x200x4_Color_31: db 0x2A,0x3F,0x3F
  PALETTE_320x200x4_Color_32: db 0x15,0x0,0x0
  PALETTE_320x200x4_Color_33: db 0x15,0x0,0x2A
  PALETTE_320x200x4_Color_34: db 0x15,0x2A,0x0
  PALETTE_320x200x4_Color_35: db 0x15,0x2A,0x2A
  PALETTE_320x200x4_Color_36: db 0x3F,0x0,0x0
  PALETTE_320x200x4_Color_37: db 0x3F,0x0,0x2A
  PALETTE_320x200x4_Color_38: db 0x3F,0x2A,0x0
  PALETTE_320x200x4_Color_39: db 0x3F,0x2A,0x2A
  PALETTE_320x200x4_Color_40: db 0x15,0x0,0x15
  PALETTE_320x200x4_Color_41: db 0x15,0x0,0x3F
  PALETTE_320x200x4_Color_42: db 0x15,0x2A,0x15
  PALETTE_320x200x4_Color_43: db 0x15,0x2A,0x3F
  PALETTE_320x200x4_Color_44: db 0x3F,0x0,0x15
  PALETTE_320x200x4_Color_45: db 0x3F,0x0,0x3F
  PALETTE_320x200x4_Color_46: db 0x3F,0x2A,0x15
  PALETTE_320x200x4_Color_47: db 0x3F,0x2A,0x3F
  PALETTE_320x200x4_Color_48: db 0x15,0x15,0x0
  PALETTE_320x200x4_Color_49: db 0x15,0x15,0x2A
  PALETTE_320x200x4_Color_50: db 0x15,0x3F,0x0
  PALETTE_320x200x4_Color_51: db 0x15,0x3F,0x2A
  PALETTE_320x200x4_Color_52: db 0x3F,0x15,0x0
  PALETTE_320x200x4_Color_53: db 0x3F,0x15,0x2A
  PALETTE_320x200x4_Color_54: db 0x3F,0x3F,0x0
  PALETTE_320x200x4_Color_55: db 0x3F,0x3F,0x2A
  PALETTE_320x200x4_Color_56: db 0x15,0x15,0x15
  PALETTE_320x200x4_Color_57: db 0x15,0x15,0x3F
  PALETTE_320x200x4_Color_58: db 0x15,0x3F,0x15
  PALETTE_320x200x4_Color_59: db 0x15,0x3F,0x3F
  PALETTE_320x200x4_Color_60: db 0x3F,0x15,0x15
  PALETTE_320x200x4_Color_61: db 0x3F,0x15,0x3F
  PALETTE_320x200x4_Color_62: db 0x3F,0x3F,0x15
  PALETTE_320x200x4_Color_63: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_64: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_65: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_66: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_67: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_68: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_69: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_70: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_71: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_72: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_73: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_74: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_75: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_76: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_77: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_78: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_79: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_80: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_81: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_82: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_83: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_84: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_85: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_86: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_87: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_88: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_89: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_90: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_91: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_92: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_93: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_94: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_95: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_96: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_97: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_98: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_99: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_100: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_101: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_102: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_103: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_104: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_105: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_106: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_107: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_108: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_109: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_110: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_111: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_112: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_113: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_114: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_115: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_116: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_117: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_118: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_119: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_120: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_121: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_122: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_123: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_124: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_125: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_126: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_127: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_128: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_129: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_130: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_131: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_132: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_133: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_134: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_135: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_136: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_137: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_138: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_139: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_140: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_141: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_142: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_143: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_144: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_145: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_146: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_147: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_148: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_149: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_150: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_151: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_152: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_153: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_154: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_155: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_156: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_157: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_158: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_159: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_160: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_161: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_162: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_163: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_164: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_165: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_166: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_167: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_168: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_169: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_170: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_171: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_172: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_173: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_174: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_175: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_176: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_177: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_178: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_179: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_180: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_181: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_182: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_183: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_184: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_185: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_186: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_187: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_188: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_189: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_190: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_191: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_192: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_193: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_194: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_195: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_196: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_197: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_198: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_199: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_200: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_201: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_202: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_203: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_204: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_205: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_206: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_207: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_208: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_209: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_210: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_211: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_212: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_213: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_214: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_215: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_216: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_217: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_218: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_219: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_220: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_221: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_222: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_223: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_224: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_225: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_226: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_227: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_228: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_229: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_230: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_231: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_232: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_233: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_234: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_235: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_236: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_237: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_238: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_239: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_240: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_241: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_242: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_243: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_244: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_245: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_246: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_247: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_248: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_249: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_250: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_251: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_252: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_253: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_254: db 0x3F,0x3F,0x3F
  PALETTE_320x200x4_Color_255: db 0x3F,0x3F,0x3F


Last edited by ~ on Tue May 24, 2016 3:00 pm, edited 3 times in total.
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Register Values for Mode 4h (Default text font)

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Default Text Font, Mode 4h, Graphics, 320x200x4 Colors, CGA

This is a graphics mode so it doesn't use text fonts.

Instead you'll need direct drawing techniques along with the default font to get text with your own routines. We don't provide it here (it would be part of a drawing tutorial).

Anyway, in this mode we would effectively get a text area with a 40x12x16 colors resolution implemented in software.
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Register Values for Mode 12h (Registers)

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Register Values, Mode 12h, Graphics, 640x480x16 Colors, VGA

Code: Select all

;Version 2013-03-10
;;

VGA_640x480x16Gen__MiscOutputReg:
;General Register, Miscellaneous Output (W; 0x3C2):
;;
 ;
 ;  Bits:
 ;      0 -- I/O Address select
 ;           Color Emulation  (1) or Monochrome Emulation   (0)
 ;
 ;      1 -- Enable RAM
 ;           Enable video RAM (1) or Disable address decode (0)
 ;
 ;    2,3 -- Clock Select - ??? - I currently don't know where is the CS2 bit
 ;                                so I don't know what configuration is selected here
 ;           CS2  CS1  CS0  Clock
 ;           ---  ---  ---  -----
 ;            0    0    0   25.175 MHz    ;<--this one!!!!!!!
 ;            0    0    1   28.322 MHz
 ;         -------------------------------Below this line, consider Oak-specific values
 ;            0    1    0   65 MHz (external clock per true VGA standard)
 ;            0    1    1   44.9 MHz (undefined per true VGA standard)
 ;            1    0    0   14.161 MHz (derived from 28.322 MHz)
 ;            1    0    1   18 MHz (derived from 36 MHz)
 ;            1    1    0   40 MHz
 ;            1    1    1   36 MHz
 ;
 ;      4 -- Reserved
 ;            (0)
 ;
 ;      5 -- Page bit for odd/even
 ;           High 64K         (1) or Low 64K                (0) page of memory
 ;
 ;      6 -- Horizontal Sync Polarity
 ;           Negative         (1) or Posite Vertic. Retrace (0)
 ;
 ;      7 -- Vertical Sync Polarity
 ;           Positive         (0) or Negative Vert. Retrace (0)
 ;
 ;      Bits 7-6
 ;      --------
 ;            00 -- reserved
 ;            01 -- 400 lines
 ;            10 -- 350 lines
 ;            11 -- 480 lines     ;<-- This one!
 ;
 ;
 ;
 ;
 ;
 ;;
  db 11100011b   ;0xE3










VGA_640x480x16Gen__FeatureControlReg:
;General Register, Feature Control (RW; 0x3DA color; 0x3BA mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      3 -- Vertical Sync Select
 ;           Normal (0) or Logical OR of Vertical Sync End/Vertical Display Enable (1)
 ;
 ;      All other bits are Reserved
 ;
 ;;
  db 00000000b       ;0x00




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VGA_640x480x16SequencerRegs:
;Sequencer Register, Index 0, Reset Register (RW; 0x3C4=0; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Asynchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      1 -- Synchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      All other bits are reserved
 ;;
   db 00000011b    ;0x03









;Sequencer Register, Index 1, Clocking Mode Register (RW; 0x3C4=1; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- 8/9 dot clocks
 ;           Eight dots (1) or Nine Clocks (0)
 ;
 ;      1 -- Reserved
 ;
 ;      2 -- Shift Load
 ;           If bit 4 is 0:
 ;           Reload serializers each char clock (0) or on every other (1)
 ;
 ;      3 -- Dot clock
 ;           Normal clock (0) or divide clock by 2 (1)
 ;
 ;      4 -- Shift 4
 ;           Reload serializers each char clock (0) or on each fourth (1)
 ;
 ;      5 -- Screen off
 ;           Video screen off and max mem bandwidth to CPU (1) or Normal operation (0)
 ;
 ;    6-7 -- Reserved
 ;;
  db 00100001b       ;0x21









;Sequencer Register, Index 2, Map Mask Register (RW; 0x3C4=2; 0x3C5):
;;
 ;
 ;  Bits:
 ;    0-3 -- Map mask
 ;           Enable (1) or disable writes (0) to the corresponding map, 0-3, with bits 0-3
 ;
 ;    All other bits are reserved.
 ;;
  db 00001111b       ;0x0F










;Sequencer Register, Index 3, Character Map Select Register (RW; 0x3C4=3; 0x3C5):
;;
 ;
 ;  Bits:
 ;    4,1,0 -- Character Map Select B
 ;             000
 ;             1st 8K of Map 2
 ;
 ;    5,3,2 -- Character Map Select A
 ;             000
 ;             1st 8K of Map 2
 ;             NOTE: The value of Character Map Select A == Character Map Select B,
 ;                   so we will ignore Character Map Select A and use
 ;                   Character Map Select B configuration.
 ;
 ;    All other bits are reserved.
 ;;
  db 00000000b       ;0x00










;Sequencer Register, Index 4, Memory Mode Register (RW; 0x3C4=4; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Reserved
 ;
 ;      1 -- Extended Memory (1)
 ;           0 -- No extended memory present (less than 64K)
 ;           1 -- Extended memory present (more than 64K; use 256K;
 ;                also enables the Character Map Select feature)
 ;
 ;      2 -- Odd/Even (1)
 ;           0 -- Direct even addresses to maps 0 and 2 and odd addresses
 ;                to maps 1 and 3.
 ;           1 -- If bit 3 is 0: make the CPU access data sequentially
 ;                within a bit map.
 ;
 ;      3 -- Chain-4 (1)
 ;           0 -- If bit 2 is 1, make the CPU access data sequentially within
 ;                a bit map by the Map Mask Register.
 ;           1 -- Make the two lower address bits to select the map that will
 ;                be accessed.
 ;
 ;
 ;    4-7 -- Reserved
 ;;
  db 00000110b       ;0x06




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VGA_640x480x16CRTCRegs:
;CRTC Controller, Index 0, Horizontal Total (RW; 0x3D4=0 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of horizontal characters MINUS 5
 ;;
  db 95              ;0x5F










;CRTC Controller, Index 1, Horizontal Display-Enable End (RW; 0x3D4=1 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 79              ;0x4F










;CRTC Controller, Index 2, Start Horizontal Blanking Register (RW; 0x3D4=2 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 01010000b       ;0x50










;CRTC Controller, Index 3, End Horizontal Blanking Register (RW; 0x3D4=3 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Blanking (2 here)
 ;
 ;      5,6 -- Display Enable Skew Control (0 here)
 ;
 ;        7 -- Test bit; must be 1
 ;;
  db 10000010b       ;0x82











;CRTC Controller, Index 4, Start Horizontal Retrace Pulse (RW; 0x3D4=4 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Start Horizontal Retrace Pulse (84 here)
 ;;
  db 01010100b       ;0x54












;CRTC Controller, Index 5, End Horizontal Retrace Pulse (RW; 0x3D4=5 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Retrace
 ;      5-6 -- Horizontal Retrace Delay
 ;        7 -- End Horizontal Blanking, Bit 5
 ;;
  db 10000000b       ;0x80











;CRTC Controller, Index 6, Vertical Total (RW; 0x3D4=6 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- 8 lower bits of number of horizontal raster scans MINUS 2
 ;;
  db 00001011b       ;0x0B










;CRTC Controller, Index 7, Overflow (RW; 0x3D4=7 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- bit 8 of vertical total, reg idx 0x06
 ;      1 -- bit 8 of vertical total, reg idx 0x12
 ;      2 -- bit 8 of vertical total, reg idx 0x10
 ;      3 -- bit 8 of vertical total, reg idx 0x15
 ;      4 -- bit 8 of vertical total, reg idx 0x18
 ;      5 -- bit 9 of vertical total, reg idx 0x06
 ;      6 -- bit 9 of vertical total, reg idx 0x12
 ;      7 -- bit 9 of vertical total, reg idx 0x10
 ;;
  db 00111110b       ;0x3E











;CRTC Controller, Index 8, Preset Row Scan (RW; 0x3D4=8 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- preset row scan
 ;      5-6 -- byte panning control
 ;      7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 9, Maximum Scan Line (RW; 0x3D4=9 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- maximum scan line
 ;        5 -- start vertical blank
 ;        6 -- line compare
 ;        7 -- 200 to 400 line conversion
 ;;
  db 01000000b       ;0x40










;CRTC Controller, Index 10, Cursor Start (RW; 0x3D4=0x0A color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor start
 ;        5 -- cursor off
 ;      6-7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 11, Cursor End (RW; 0x3D4=0x0B color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor end
 ;      5-6 -- cursor skew
 ;        7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 12, Start Address High (RW; 0x3D4=0x0C color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 13, Start Address Low (RW; 0x3D4=0x0D color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address low
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 14, Cursor Location High (RW; 0x3D4=0x0E color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 15, Cursor Location Low (RW; 0x3D4=0x0F color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor low
 ;;
  db 89              ;0x59









;CRTC Controller, Index 16, Vertical Retrace Start (W; 0x3D4=0x10 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 - lower 8 bits of vertical retrace pulse start position
 ;;
  db 234             ;0xEA










;CRTC Controller, Index 17, Vertical Retrace End (W; 0x3D4=0x11 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- vertical retrace end
 ;        4 -- clear vertical interrupt
 ;        5 -- enable vertical interrupt
 ;        6 -- select 5 refresh cycles
 ;        7 -- protect registers 0 to 7 enabled (0) or disabled (1)
 ;;
  db 10001100b       ;0x8C










;CRTC Controller, Index 18, Vertical Display Enable End (RW; 0x3D4=0x12 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- vertical display enable end
 ;;
  db 223             ;0xDF










;CRTC Controller, Index 19, Logical Width, aka Offset (RW; 0x3D4=0x13 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- offset
 ;;
  db 40              ;0x28










;CRTC Controller, Index 20, Underline Location (RW; 0x3D4=0x14 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- underline location
 ;        5 -- count by 4
 ;        6 -- double word mode
 ;        7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 21, Start Vertical Blanking (RW; 0x3D4=0x15 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start vertical blank -- lower 8 bits of 10-bit register
 ;;
  db 231             ;0xE7










;CRTC Controller, Index 22, End Vertical Blanking (RW; 0x3D4=0x16 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- end vertical blank
 ;;
  db 4               ;0x04










;CRTC Controller, Index 23, CRTC Mode Control (RW; 0x3D4=0x17 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- compatibility mode support
 ;      1 -- select row scan counter
 ;      2 -- horizontal retrace select
 ;      3 -- count by two
 ;      4 -- reserved
 ;      5 -- address wrap
 ;      6 -- word mode (0) or byte mode (1)
 ;      7 -- hardware reset
 ;;
  db 11100011b       ;0xE3










;CRTC Controller, Index 24, Line Compare (RW; 0x3D4=0x18 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- lower 8 bits of compare target.
 ;             Bit 8 is in Overflow register index 7.
 ;             Bit 9 is in Maximum Scan Line register index 9. 
 ;;
  db 11111111b       ;0xFF




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VGA_640x480x16GraphicsRegs:
;Graphics Controller Register, Index 0, Set/Reset (RW; 0x3CE=0; 0x3CF):
;;
 ;
 ;  Bits:
 ;      0-3 -- Set/Reset
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 1, Enable Set/Reset (RW; 0x3CE=1; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Enable Set/Reset
 ;             1 -- If write mode is 0, and the bit for the map is 1 here,
 ;                  write memory address with the value of the Set/Reset register.
 ;
 ;             0 -- If write mode is 0, and the bit for the map is 0 here,
 ;                  write memory address with the value of system CPU.
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 2, Color Compare (RW; 0x3CE=2; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Color compare
 ;             Color Compare Map n, where n is the bit position
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 3, Data Rotate (RW; 0x3CE=3; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-2 -- Data rotate
 ;             Number of bits to right-rotate CPU data (0 here)
 ;
 ;      3,4 -- Function select
 ;             00 -- unmodified   <-- this one!!!!!!
 ;             01 -- AND data with latch
 ;             10 -- OR data with latch
 ;             11 -- XOR data with latch
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 4, Read Map Select (RW; 0x3CE=4; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Read Map Select
 ;             Select maps 0 to 3 for system read operations (map 0 here)
 ;
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000011b       ;0x03










;Graphics Controller Register, Index 5, Graphics Mode (RW; 0x3CE=5; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Write Mode
 ;             Select write mode 0 to 3 (0 here)
 ;
 ;        2 -- Reserved, undefined on read
 ;
 ;        3 -- Read Type
 ;
 ;        4 -- Odd/Even
 ;
 ;        5 -- Shift Register
 ;
 ;        6 -- 256 Color Mode
 ;
 ;        7 -- Reserved
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 6, Miscellaneous (RW; 0x3CE=6; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;        0 -- Graphics Mode
 ;             Graphics Mode (1) or Text Mode (0)
 ;
 ;        1 -- Odd/Even
 ;
 ;      2,3 -- Memory Map (1 here)
 ;                    Map 0 -- 0xA0000-0xBFFFF
 ;                    Map 1 -- 0xA0000-0xAFFFF
 ;                    Map 2 -- 0xB0000-0xBFFFF
 ;                    Map 3 -- 0xB8000-0xBFFFF
 ;
 ;      4-7 -- Reserved
 ;;
  db 00000101b       ;0x05










;Graphics Controller Register, Index 7, Color Don't Care (RW; 0x3CE=7; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- For each bit, if 0, don't participate in color
 ;             compare cycle; if 1 participate in it for that map.
 ;;
  db 00001111b       ;0x0F










;Graphics Controller Register, Index 8, Bit Mask (RW; 0x3CE=8; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Bit mask
 ;;
  db 11111111b       ;0xFF




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VGA_640x480x16AttributeRegs:
;Attribute Controller Register, Index 0, Palette 0 (RW; 0x3C0=0; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 0               ;0x00










;Attribute Controller Register, Index 1, Palette 1 (RW; 0x3C0=1; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 1               ;0x01










;Attribute Controller Register, Index 2, Palette 2 (RW; 0x3C0=2; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 2               ;0x02










;Attribute Controller Register, Index 3, Palette 3 (RW; 0x3C0=3; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 3               ;0x03










;Attribute Controller Register, Index 4, Palette 4 (RW; 0x3C0=4; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 4               ;0x04










;Attribute Controller Register, Index 5, Palette 5 (RW; 0x3C0=5; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 5               ;0x05










;Attribute Controller Register, Index 6, Palette 6 (RW; 0x3C0=6; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 20              ;0x14










;Attribute Controller Register, Index 7, Palette 7 (RW; 0x3C0=7; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 7               ;0x07










;Attribute Controller Register, Index 8, Palette 8 (RW; 0x3C0=8; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 56              ;0x38










;Attribute Controller Register, Index 9, Palette 9 (RW; 0x3C0=9; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 57              ;0x39










;Attribute Controller Register, Index 10, Palette 10 (RW; 0x3C0=0x0A; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 58              ;0x3A










;Attribute Controller Register, Index 11, Palette 11 (RW; 0x3C0=0x0B; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 59              ;0x3B










;Attribute Controller Register, Index 12, Palette 12 (RW; 0x3C0=0x0C; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 60              ;0x3C










;Attribute Controller Register, Index 13, Palette 13 (RW; 0x3C0=0x0D; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 61              ;0x3D










;Attribute Controller Register, Index 14, Palette 14 (RW; 0x3C0=0x0E; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 62              ;0x3E










;Attribute Controller Register, Index 15, Palette 15 (RW; 0x3C0=0x0F; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 63 color value
 ;
 ;      All other bits are reserved
 ;;
  db 63              ;0x3F










;Attribute Controller, Index 16, Attribute Mode Control (RW; 0x3C0=0x10; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- graphics/alphanumeric
 ;      1 -- mono emulation
 ;      2 -- enable line graphics character codes
 ;      3 -- enable blink/select background intensity
 ;      4 -- reserved
 ;      5 -- PEL panning compatibility
 ;      6 -- PEL width
 ;      7 -- P5, P4 select
 ;
 ;;
  db 00000001b       ;0x01










;Attribute Controller, Index 17, Overscan Color (RW; 0x3C0=0x11; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- overscan color
 ;
 ;;
  db 00000000b       ;0x00 or black










;Attribute Controller, Index 18, Color Plane Enable (RW; 0x3C0=0x12; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- enable color plane
 ;      4-5 -- video status MUX
 ;      6-7 -- reserved
 ;
 ;;
  db 00001111b       ;0x0F










;Attribute Controller, Index 19, Horizontal PEL Panning (RW; 0x3C0=0x13; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- horizontal PEL panning
 ;      4-7 -- reserved
 ;
 ;;
  db 00000000b       ;0x00










;Attribute Controller, Index 20, Color Select (RW; 0x3C0=0x14; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- SC5,SC4
 ;      2-3 -- SC6,SC7
 ;      4-7 -- Reserved
 ;
 ;;
  db 00000000b       ;0x00


Last edited by ~ on Tue May 24, 2016 3:00 pm, edited 1 time in total.
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Register Values for Mode 12h (256-color palette)

Post by ~ »

Palette, Mode 12h, Graphics, 640x480x16 Colors, VGA

This one also seems to be the same palette for Text Mode 80x25x16 Colors.

It looks like all standard 4-color and 16-color CGA/EGA/VGA modes use the exact same default palette from the BIOS, so in the final code we will only include a single palette for that called PALETTE256_4_16_colors.

It's a 16-color mode, so the palette indexes into the 256-color palette are integrated into 16 color registers in the main VGA register set. Also, only the first 16 colors are used.

Howevever, every color index can select between 64 different colors, but there are just 16 colors selected at a time on screen.

The palette below contains 64 different colors.

Code: Select all

;Version 2013-03-10
;;

PALETTE_640x400x16:
  PALETTE_640x400x16_Color_0: db 0x0,0x0,0x0
  PALETTE_640x400x16_Color_1: db 0x0,0x0,0x2A
  PALETTE_640x400x16_Color_2: db 0x0,0x2A,0x0
  PALETTE_640x400x16_Color_3: db 0x0,0x2A,0x2A
  PALETTE_640x400x16_Color_4: db 0x2A,0x0,0x0
  PALETTE_640x400x16_Color_5: db 0x2A,0x0,0x2A
  PALETTE_640x400x16_Color_6: db 0x2A,0x2A,0x0
  PALETTE_640x400x16_Color_7: db 0x2A,0x2A,0x2A
  PALETTE_640x400x16_Color_8: db 0x0,0x0,0x15
  PALETTE_640x400x16_Color_9: db 0x0,0x0,0x3F
  PALETTE_640x400x16_Color_10: db 0x0,0x2A,0x15
  PALETTE_640x400x16_Color_11: db 0x0,0x2A,0x3F
  PALETTE_640x400x16_Color_12: db 0x2A,0x0,0x15
  PALETTE_640x400x16_Color_13: db 0x2A,0x0,0x3F
  PALETTE_640x400x16_Color_14: db 0x2A,0x2A,0x15
  PALETTE_640x400x16_Color_15: db 0x2A,0x2A,0x3F
  PALETTE_640x400x16_Color_16: db 0x0,0x15,0x0
  PALETTE_640x400x16_Color_17: db 0x0,0x15,0x2A
  PALETTE_640x400x16_Color_18: db 0x0,0x3F,0x0
  PALETTE_640x400x16_Color_19: db 0x0,0x3F,0x2A
  PALETTE_640x400x16_Color_20: db 0x2A,0x15,0x0
  PALETTE_640x400x16_Color_21: db 0x2A,0x15,0x2A
  PALETTE_640x400x16_Color_22: db 0x2A,0x3F,0x0
  PALETTE_640x400x16_Color_23: db 0x2A,0x3F,0x2A
  PALETTE_640x400x16_Color_24: db 0x0,0x15,0x15
  PALETTE_640x400x16_Color_25: db 0x0,0x15,0x3F
  PALETTE_640x400x16_Color_26: db 0x0,0x3F,0x15
  PALETTE_640x400x16_Color_27: db 0x0,0x3F,0x3F
  PALETTE_640x400x16_Color_28: db 0x2A,0x15,0x15
  PALETTE_640x400x16_Color_29: db 0x2A,0x15,0x3F
  PALETTE_640x400x16_Color_30: db 0x2A,0x3F,0x15
  PALETTE_640x400x16_Color_31: db 0x2A,0x3F,0x3F
  PALETTE_640x400x16_Color_32: db 0x15,0x0,0x0
  PALETTE_640x400x16_Color_33: db 0x15,0x0,0x2A
  PALETTE_640x400x16_Color_34: db 0x15,0x2A,0x0
  PALETTE_640x400x16_Color_35: db 0x15,0x2A,0x2A
  PALETTE_640x400x16_Color_36: db 0x3F,0x0,0x0
  PALETTE_640x400x16_Color_37: db 0x3F,0x0,0x2A
  PALETTE_640x400x16_Color_38: db 0x3F,0x2A,0x0
  PALETTE_640x400x16_Color_39: db 0x3F,0x2A,0x2A
  PALETTE_640x400x16_Color_40: db 0x15,0x0,0x15
  PALETTE_640x400x16_Color_41: db 0x15,0x0,0x3F
  PALETTE_640x400x16_Color_42: db 0x15,0x2A,0x15
  PALETTE_640x400x16_Color_43: db 0x15,0x2A,0x3F
  PALETTE_640x400x16_Color_44: db 0x3F,0x0,0x15
  PALETTE_640x400x16_Color_45: db 0x3F,0x0,0x3F
  PALETTE_640x400x16_Color_46: db 0x3F,0x2A,0x15
  PALETTE_640x400x16_Color_47: db 0x3F,0x2A,0x3F
  PALETTE_640x400x16_Color_48: db 0x15,0x15,0x0
  PALETTE_640x400x16_Color_49: db 0x15,0x15,0x2A
  PALETTE_640x400x16_Color_50: db 0x15,0x3F,0x0
  PALETTE_640x400x16_Color_51: db 0x15,0x3F,0x2A
  PALETTE_640x400x16_Color_52: db 0x3F,0x15,0x0
  PALETTE_640x400x16_Color_53: db 0x3F,0x15,0x2A
  PALETTE_640x400x16_Color_54: db 0x3F,0x3F,0x0
  PALETTE_640x400x16_Color_55: db 0x3F,0x3F,0x2A
  PALETTE_640x400x16_Color_56: db 0x15,0x15,0x15
  PALETTE_640x400x16_Color_57: db 0x15,0x15,0x3F
  PALETTE_640x400x16_Color_58: db 0x15,0x3F,0x15
  PALETTE_640x400x16_Color_59: db 0x15,0x3F,0x3F
  PALETTE_640x400x16_Color_60: db 0x3F,0x15,0x15
  PALETTE_640x400x16_Color_61: db 0x3F,0x15,0x3F
  PALETTE_640x400x16_Color_62: db 0x3F,0x3F,0x15
  PALETTE_640x400x16_Color_63: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_64: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_65: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_66: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_67: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_68: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_69: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_70: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_71: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_72: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_73: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_74: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_75: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_76: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_77: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_78: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_79: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_80: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_81: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_82: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_83: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_84: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_85: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_86: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_87: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_88: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_89: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_90: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_91: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_92: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_93: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_94: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_95: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_96: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_97: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_98: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_99: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_100: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_101: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_102: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_103: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_104: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_105: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_106: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_107: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_108: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_109: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_110: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_111: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_112: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_113: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_114: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_115: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_116: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_117: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_118: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_119: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_120: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_121: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_122: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_123: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_124: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_125: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_126: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_127: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_128: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_129: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_130: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_131: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_132: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_133: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_134: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_135: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_136: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_137: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_138: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_139: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_140: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_141: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_142: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_143: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_144: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_145: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_146: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_147: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_148: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_149: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_150: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_151: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_152: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_153: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_154: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_155: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_156: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_157: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_158: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_159: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_160: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_161: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_162: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_163: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_164: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_165: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_166: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_167: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_168: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_169: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_170: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_171: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_172: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_173: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_174: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_175: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_176: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_177: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_178: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_179: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_180: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_181: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_182: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_183: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_184: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_185: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_186: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_187: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_188: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_189: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_190: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_191: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_192: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_193: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_194: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_195: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_196: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_197: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_198: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_199: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_200: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_201: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_202: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_203: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_204: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_205: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_206: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_207: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_208: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_209: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_210: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_211: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_212: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_213: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_214: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_215: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_216: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_217: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_218: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_219: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_220: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_221: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_222: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_223: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_224: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_225: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_226: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_227: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_228: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_229: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_230: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_231: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_232: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_233: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_234: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_235: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_236: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_237: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_238: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_239: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_240: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_241: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_242: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_243: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_244: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_245: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_246: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_247: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_248: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_249: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_250: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_251: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_252: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_253: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_254: db 0x3F,0x3F,0x3F
  PALETTE_640x400x16_Color_255: db 0x3F,0x3F,0x3F


Last edited by ~ on Tue May 24, 2016 2:59 pm, edited 1 time in total.
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Register Values for Mode 12h (Default text font)

Post by ~ »

Default Text Font, Mode 12h, Graphics, 640x480x16 Colors, VGA

This is a graphics mode so it doesn't use text fonts.

Instead you'll need direct drawing techniques along with the default font to get text with your own routines. We don't provide it here (it would be part of a drawing tutorial).

Anyway, in this mode we would effectively get a text area with an 80x30x16 colors resolution implemented in software.
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Re: Implementing a Function to Switch Standard VGA Video Mod

Post by iansjack »

Is a forum post the best place for this sort of stuff? Wouldn't it be better in the Wiki?
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Re: Implementing a Function to Switch Standard VGA Video Mod

Post by ~ »

iansjack wrote:Is a forum post the best place for this sort of stuff? Wouldn't it be better in the Wiki?
I feel that posting full, clear and packed code in this tutorialized way allows for fast discussions and the resulting improvements and fixes, and also makes it more visible.

Once a topic has been discussed, reviewed and made more popular, it can be taken anywhere knowing that it's right.

It will surely help to feed the forum again with useful snippets that can be compiled into an interesting test, beyond most topics now which only contain partial code and problems specific to that code.

It will make improve the forum quality and contain more useful basic stuff to solve it and provide enough material to stop repeating partial solutions on the basics.


I always also get into the dilemma of whether it's better to work with individual HTML files that are nicely formatted and that don't require a database, or working in a forum or in a Wiki. In the end it seems to be better to use the media that allows the most immediate discussion and also a version in HTML that can be downloaded and compiled.

Then it can be back-linked in several parts of the Wiki. It's nice having a bit of variety.
Last edited by ~ on Tue May 24, 2016 4:11 pm, edited 1 time in total.
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Register Values for Mode 13h (Registers)

Post by ~ »

Register Values, Mode 13h, Graphics, 320x200x256 Colors, MCGA

Code: Select all

;Version 2013-03-10
;;

MCGA_320x200x256Gen__MiscOutputReg:
;General Register, Miscellaneous Output (W; 0x3C2):
;;
 ;
 ;  Bits:
 ;      0 -- I/O Address select
 ;           Color Emulation  (1) or Monochrome Emulation   (0)
 ;
 ;      1 -- Enable RAM
 ;           Enable video RAM (1) or Disable address decode (0)
 ;
 ;    2,3 -- Clock Select - ??? - I currently don't know where is the CS2 bit
 ;                                so I don't know what configuration is selected here
 ;           CS2  CS1  CS0  Clock
 ;           ---  ---  ---  -----
 ;            0    0    0   25.175 MHz    ;<--this one!!!!!!!
 ;            0    0    1   28.322 MHz
 ;         -------------------------------Below this line, consider Oak-specific values
 ;            0    1    0   65 MHz (external clock per true VGA standard)
 ;            0    1    1   44.9 MHz (undefined per true VGA standard)
 ;            1    0    0   14.161 MHz (derived from 28.322 MHz)
 ;            1    0    1   18 MHz (derived from 36 MHz)
 ;            1    1    0   40 MHz
 ;            1    1    1   36 MHz
 ;
 ;      4 -- Reserved
 ;            (0)
 ;
 ;      5 -- Page bit for odd/even
 ;           High 64K         (1) or Low 64K                (0) page of memory
 ;
 ;      6 -- Horizontal Sync Polarity
 ;           Negative         (1) or Posite Vertic. Retrace (0)
 ;
 ;      7 -- Vertical Sync Polarity
 ;           Positive         (0) or Negative Vert. Retrace (0)
 ;
 ;      Bits 7-6
 ;      --------
 ;            00 -- reserved
 ;            01 -- 400 lines     ;<-- This one!
 ;            10 -- 350 lines
 ;            11 -- 480 lines
 ;
 ;
 ;
 ;
 ;
 ;;
  db 01100011b       ;0x63










MCGA_320x200x256Gen__FeatureControlReg:
;General Register, Feature Control (RW; 0x3DA color; 0x3BA mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      3 -- Vertical Sync Select
 ;           Normal (0) or Logical OR of Vertical Sync End/Vertical Display Enable (1)
 ;
 ;      All other bits are Reserved
 ;
 ;;
  db 00000000b       ;0x00




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MCGA_320x200x256SequencerRegs:
;Sequencer Register, Index 0, Reset Register (RW; 0x3C4=0; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Asynchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      1 -- Synchronous Reset
 ;           Operating  (1) or Reset   (0)
 ;
 ;      All other bits are reserved
 ;;
  db 00000011b       ;0x03










;Sequencer Register, Index 1, Clocking Mode Register (RW; 0x3C4=1; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- 8/9 dot clocks
 ;           Eight dots (1) or Nine Clocks (0)
 ;
 ;      1 -- Reserved
 ;
 ;      2 -- Shift Load
 ;           If bit 4 is 0:
 ;           Reload serializers each char clock (0) or on every other (1)
 ;
 ;      3 -- Dot clock
 ;           Normal clock (0) or divide clock by 2 (1)
 ;
 ;      4 -- Shift 4
 ;           Reload serializers each char clock (0) or on each fourth (1)
 ;
 ;      5 -- Screen off
 ;           Video screen off and max mem bandwidth to CPU (1) or Normal operation (0)
 ;
 ;    6-7 -- Reserved
 ;;
  db 00100001b       ;0x21   ---- Modified










;Sequencer Register, Index 2, Map Mask Register (RW; 0x3C4=2; 0x3C5):
;;
 ;
 ;  Bits:
 ;    0-3 -- Map mask
 ;           Enable (1) or disable writes (0) to the corresponding map, 0-3, with bits 0-3
 ;
 ;    All other bits are reserved.
 ;;
  db 00001111b       ;0x0F










;Sequencer Register, Index 3, Character Map Select Register (RW; 0x3C4=3; 0x3C5):
;;
 ;
 ;  Bits:
 ;    4,1,0 -- Character Map Select B
 ;             000
 ;             1st 8K of Map 2
 ;
 ;    5,3,2 -- Character Map Select A
 ;             000
 ;             1st 8K of Map 2
 ;             NOTE: The value of Character Map Select A == Character Map Select B,
 ;                   so we will ignore Character Map Select A and use
 ;                   Character Map Select B configuration.
 ;
 ;    All other bits are reserved.
 ;;
  db 00000000b       ;0x00










;Sequencer Register, Index 4, Memory Mode Register (RW; 0x3C4=4; 0x3C5):
;;
 ;
 ;  Bits:
 ;      0 -- Reserved
 ;
 ;      1 -- Extended Memory (1)
 ;           0 -- No extended memory present (less than 64K)
 ;           1 -- Extended memory present (more than 64K; use 256K;
 ;                also enables the Character Map Select feature)
 ;
 ;      2 -- Odd/Even (1)
 ;           0 -- Direct even addresses to maps 0 and 2 and odd addresses
 ;                to maps 1 and 3.
 ;           1 -- If bit 3 is 0: make the CPU access data sequentially
 ;                within a bit map.
 ;
 ;      3 -- Chain-4 (1)
 ;           0 -- If bit 2 is 1, make the CPU access data sequentially within
 ;                a bit map by the Map Mask Register.
 ;           1 -- Make the two lower address bits to select the map that will
 ;                be accessed.
 ;
 ;
 ;    4-7 -- Reserved
 ;;
  db 00001110b       ;0x0E




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MCGA_320x200x256CRTCRegs:
;CRTC Controller, Index 0, Horizontal Total (RW; 0x3D4=0 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of horizontal characters MINUS 5
 ;;
  db 95              ;0x5F










;CRTC Controller, Index 1, Horizontal Display-Enable End (RW; 0x3D4=1 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 79              ;0x4F










;CRTC Controller, Index 2, Start Horizontal Blanking Register (RW; 0x3D4=2 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Number of total displayed characters MINUS 1
 ;;
  db 01010000b       ;0x50










;CRTC Controller, Index 3, End Horizontal Blanking Register (RW; 0x3D4=3 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Blanking (2 here)
 ;
 ;      5,6 -- Display Enable Skew Control (0 here)
 ;
 ;        7 -- Test bit; must be 1
 ;;
  db 10000010b       ;0x82










;CRTC Controller, Index 4, Start Horizontal Retrace Pulse (RW; 0x3D4=4 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Start Horizontal Retrace Pulse (84 here)
 ;;
  db 01010100b       ;0x54










;CRTC Controller, Index 5, End Horizontal Retrace Pulse (RW; 0x3D4=5 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- End Horizontal Retrace
 ;      5-6 -- Horizontal Retrace Delay
 ;        7 -- End Horizontal Blanking, Bit 5
 ;;
  db 10000000b       ;0x80










;CRTC Controller, Index 6, Vertical Total (RW; 0x3D4=6 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- 8 lower bits of number of horizontal raster scans MINUS 2
 ;;
  db 10111111b       ;0xBF










;CRTC Controller, Index 7, Overflow (RW; 0x3D4=7 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- bit 8 of vertical total, reg idx 0x06
 ;      1 -- bit 8 of vertical total, reg idx 0x12
 ;      2 -- bit 8 of vertical total, reg idx 0x10
 ;      3 -- bit 8 of vertical total, reg idx 0x15
 ;      4 -- bit 8 of vertical total, reg idx 0x18
 ;      5 -- bit 9 of vertical total, reg idx 0x06
 ;      6 -- bit 9 of vertical total, reg idx 0x12
 ;      7 -- bit 9 of vertical total, reg idx 0x10
 ;;
  db 00011111b       ;0x1F










;CRTC Controller, Index 8, Preset Row Scan (RW; 0x3D4=8 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- preset row scan
 ;      5-6 -- byte panning control
 ;      7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 9, Maximum Scan Line (RW; 0x3D4=9 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- maximum scan line
 ;        5 -- start vertical blank
 ;        6 -- line compare
 ;        7 -- 200 to 400 line conversion
 ;;
  db 01000001b       ;0x41










;CRTC Controller, Index 10, Cursor Start (RW; 0x3D4=0x0A color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor start
 ;        5 -- cursor off
 ;      6-7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 11, Cursor End (RW; 0x3D4=0x0B color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- cursor end
 ;      5-6 -- cursor skew
 ;        7 -- reserved
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 12, Start Address High (RW; 0x3D4=0x0C color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 13, Start Address Low (RW; 0x3D4=0x0D color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start address low
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 14, Cursor Location High (RW; 0x3D4=0x0E color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor high
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 15, Cursor Location Low (RW; 0x3D4=0x0F color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- cursor low
 ;;
  db 00000000b       ;0x00










;CRTC Controller, Index 16, Vertical Retrace Start (W; 0x3D4=0x10 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 - lower 8 bits of vertical retrace pulse start position
 ;;
  db 156             ;0x9C










;CRTC Controller, Index 17, Vertical Retrace End (W; 0x3D4=0x11 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- vertical retrace end
 ;        4 -- clear vertical interrupt
 ;        5 -- enable vertical interrupt
 ;        6 -- select 5 refresh cycles
 ;        7 -- protect registers 0 to 7 enabled (0) or disabled (1)
 ;;
  db 00001110b       ;0x0E










;CRTC Controller, Index 18, Vertical Display Enable End (RW; 0x3D4=0x12 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- vertical display enable end
 ;;
  db 143             ;0x8F










;CRTC Controller, Index 19, Offset (RW; 0x3D4=0x13 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- offset
 ;;
  db 40              ;0x28










;CRTC Controller, Index 20, Underline Location (RW; 0x3D4=0x14 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-4 -- underline location
 ;        5 -- count by 4
 ;        6 -- double word mode
 ;        7 -- reserved
 ;;
  db 01000000b       ;0x40










;CRTC Controller, Index 21, Start Vertical Blanking (RW; 0x3D4=0x15 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- start vertical blank -- lower 8 bits of 10-bit register
 ;;
  db 150             ;0x96










;CRTC Controller, Index 22, End Vertical Blanking (RW; 0x3D4=0x16 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- end vertical blank
 ;;
  db 185             ;0xB9










;CRTC Controller, Index 23, CRTC Mode Control (RW; 0x3D4=0x17 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- compatibility mode support
 ;      1 -- select row scan counter
 ;      2 -- horizontal retrace select
 ;      3 -- count by two
 ;      4 -- reserved
 ;      5 -- address wrap
 ;      6 -- word mode (0) or byte mode (1)
 ;      7 -- hardware reset
 ;;
  db 10100011b       ;0xA3










;CRTC Controller, Index 24, Line Compare (RW; 0x3D4=0x18 color; 0x3B4 mono; 0x3D5 color; 0x3B5 mono):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- lower 8 bits of compare target.
 ;             Bit 8 is in Overflow register index 7.
 ;             Bit 9 is in Maximum Scan Line register index 9. 
 ;;
  db 11111111b       ;0xFF




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MCGA_320x200x256GraphicsRegs:
;Graphics Controller Register, Index 0, Set/Reset (RW; 0x3CE=0; 0x3CF):
;;
 ;
 ;  Bits:
 ;      0-3 -- Set/Reset
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 1, Enable Set/Reset (RW; 0x3CE=1; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Enable Set/Reset
 ;             1 -- If write mode is 0, and the bit for the map is 1 here,
 ;                  write memory address with the value of the Set/Reset register.
 ;
 ;             0 -- If write mode is 0, and the bit for the map is 0 here,
 ;                  write memory address with the value of system CPU.
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 2, Color Compare (RW; 0x3CE=2; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- Color compare
 ;             Color Compare Map n, where n is the bit position
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 3, Data Rotate (RW; 0x3CE=3; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-2 -- Data rotate
 ;             Number of bits to right-rotate CPU data (0 here)
 ;
 ;      3,4 -- Function select
 ;             00 -- unmodified   <-- this one!!!!!!
 ;             01 -- AND data with latch
 ;             10 -- OR data with latch
 ;             11 -- XOR data with latch
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x0










;Graphics Controller Register, Index 4, Read Map Select (RW; 0x3CE=4; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Read Map Select
 ;             Select maps 0 to 3 for system read operations (map 0 here)
 ;
 ;
 ;      All other bits are reserved. Set to 0; undefined on read.
 ;;
  db 00000000b       ;0x00










;Graphics Controller Register, Index 5, Graphics Mode (RW; 0x3CE=5; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- Write Mode
 ;             Select write mode 0 to 3 (0 here)
 ;
 ;        2 -- Reserved, undefined on read
 ;
 ;        3 -- Read Type
 ;
 ;        4 -- Odd/Even
 ;
 ;        5 -- Shift Register
 ;
 ;        6 -- 256 Color Mode
 ;
 ;        7 -- Reserved
 ;;
  db 01010000b       ;0x50










;Graphics Controller Register, Index 6, Miscellaneous (RW; 0x3CE=6; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;        0 -- Graphics Mode
 ;             Graphics Mode (1) or Text Mode (0)
 ;
 ;        1 -- Odd/Even
 ;
 ;      2,3 -- Memory Map (1 here)
 ;                    Map 0 -- 0xA0000-0xBFFFF
 ;                    Map 1 -- 0xA0000-0xAFFFF
 ;                    Map 2 -- 0xB0000-0xBFFFF
 ;                    Map 3 -- 0xB8000-0xBFFFF
 ;
 ;      4-7 -- Reserved
 ;;
  db 00000111b       ;0x07










;Graphics Controller Register, Index 7, Color Don't Care (RW; 0x3CE=7; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- For each bit, if 0, don't participate in color
 ;             compare cycle; if 1 participate in it for that map.
 ;;
  db 00001111b       ;0x0F










;Graphics Controller Register, Index 8, Bit Mask (RW; 0x3CE=8; 0x3CF):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- Bit mask
 ;;
  db 11111111b       ;0xFF




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MCGA_320x200x256AttributeRegs:
;Attribute Controller Register, Index 0, Palette 0 (RW; 0x3C0=0; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 0               ;0x00










;Attribute Controller Register, Index 1, Palette 1 (RW; 0x3C0=1; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 1               ;0x01










;Attribute Controller Register, Index 2, Palette 2 (RW; 0x3C0=2; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 2               ;0x02










;Attribute Controller Register, Index 3, Palette 3 (RW; 0x3C0=3; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 3               ;0x03










;Attribute Controller Register, Index 4, Palette 4 (RW; 0x3C0=4; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 4               ;0x04










;Attribute Controller Register, Index 5, Palette 5 (RW; 0x3C0=5; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 5               ;0x05










;Attribute Controller Register, Index 6, Palette 6 (RW; 0x3C0=6; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 6               ;0x06










;Attribute Controller Register, Index 7, Palette 7 (RW; 0x3C0=7; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 7               ;0x07










;Attribute Controller Register, Index 8, Palette 8 (RW; 0x3C0=8; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 8               ;0x08










;Attribute Controller Register, Index 9, Palette 9 (RW; 0x3C0=9; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 9               ;0x09










;Attribute Controller Register, Index 10, Palette 10 (RW; 0x3C0=0x0A; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 10              ;0x0A










;Attribute Controller Register, Index 11, Palette 11 (RW; 0x3C0=0x0B; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 11              ;0x0B










;Attribute Controller Register, Index 12, Palette 12 (RW; 0x3C0=0x0C; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 12              ;0x0C










;Attribute Controller Register, Index 13, Palette 13 (RW; 0x3C0=0x0D; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 13              ;0x0D










;Attribute Controller Register, Index 14, Palette 14 (RW; 0x3C0=0x0E; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 14              ;0x0E










;Attribute Controller Register, Index 15, Palette 15 (RW; 0x3C0=0x0F; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-5 -- 0 to 64 color value
 ;
 ;      All other bits are reserved
 ;;
  db 15              ;0x0F










;Attribute Controller, Index 16, Attribute Mode Control (RW; 0x3C0=0x10; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0 -- graphics/alphanumeric
 ;      1 -- mono emulation
 ;      2 -- enable line graphics character codes
 ;      3 -- enable blink/select background intensity
 ;      4 -- reserved
 ;      5 -- PEL panning compatibility
 ;      6 -- PEL width
 ;      7 -- P5, P4 select
 ;
 ;;
  db 01000001b       ;0x41










;Attribute Controller, Index 17, Overscan Color (RW; 0x3C0=0x11; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-7 -- overscan color
 ;
 ;;
  db 00000000b       ;0x00 or black










;Attribute Controller, Index 18, Color Plane Enable (RW; 0x3C0=0x12; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- enable color plane
 ;      4-5 -- video status MUX
 ;      6-7 -- reserved
 ;
 ;;
  db 00001111b       ;0x0F










;Attribute Controller, Index 19, Horizontal PEL Panning (RW; 0x3C0=0x13; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-3 -- horizontal PEL panning
 ;      4-7 -- reserved
 ;
 ;;
  db 00000000b       ;0x00










;Attribute Controller, Index 20, Color Select (RW; 0x3C0=0x14; write 0x3C0; read 0x3C1):
;;
 ;
 ;
 ;
 ;  Bits:
 ;      0-1 -- SC5,SC4
 ;      2-3 -- SC6,SC7
 ;      4-7 -- Reserved
 ;
 ;;
  db 00000000b       ;0x00


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Register Values for Mode 13h (256-color palette)

Post by ~ »

Palette, Mode 13h, Graphics, 320x200x256 Colors, MCGA

It looks like all standard 256-color MCGA/VGA modes use the exact same default palette from the BIOS, so in the final code we will only include a single palette for that called PALETTE256.

It's a 256-color mode, and uses the 256-color palette registers directly.

Each palette entry contains R, G and B components.
These components use up to 6 bits.
So we can select colors from a range of 18-bit colors (262,144 colors).
But we can only select and display 256 colors simultaneously.

Code: Select all

;Version 2013-03-10
;;

PALETTE_320x200x256:
  PALETTE_320x200x256_Color_0: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_1: db 0x0,0x0,0x2A
  PALETTE_320x200x256_Color_2: db 0x0,0x2A,0x0
  PALETTE_320x200x256_Color_3: db 0x0,0x2A,0x2A
  PALETTE_320x200x256_Color_4: db 0x2A,0x0,0x0
  PALETTE_320x200x256_Color_5: db 0x2A,0x0,0x2A
  PALETTE_320x200x256_Color_6: db 0x2A,0x15,0x0
  PALETTE_320x200x256_Color_7: db 0x2A,0x2A,0x2A
  PALETTE_320x200x256_Color_8: db 0x15,0x15,0x15
  PALETTE_320x200x256_Color_9: db 0x15,0x15,0x3F
  PALETTE_320x200x256_Color_10: db 0x15,0x3F,0x15
  PALETTE_320x200x256_Color_11: db 0x15,0x3F,0x3F
  PALETTE_320x200x256_Color_12: db 0x3F,0x15,0x15
  PALETTE_320x200x256_Color_13: db 0x3F,0x15,0x3F
  PALETTE_320x200x256_Color_14: db 0x3F,0x3F,0x15
  PALETTE_320x200x256_Color_15: db 0x3F,0x3F,0x3F
  PALETTE_320x200x256_Color_16: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_17: db 0x5,0x5,0x5
  PALETTE_320x200x256_Color_18: db 0x8,0x8,0x8
  PALETTE_320x200x256_Color_19: db 0xB,0xB,0xB
  PALETTE_320x200x256_Color_20: db 0xE,0xE,0xE
  PALETTE_320x200x256_Color_21: db 0x11,0x11,0x11
  PALETTE_320x200x256_Color_22: db 0x14,0x14,0x14
  PALETTE_320x200x256_Color_23: db 0x18,0x18,0x18
  PALETTE_320x200x256_Color_24: db 0x1C,0x1C,0x1C
  PALETTE_320x200x256_Color_25: db 0x20,0x20,0x20
  PALETTE_320x200x256_Color_26: db 0x24,0x24,0x24
  PALETTE_320x200x256_Color_27: db 0x28,0x28,0x28
  PALETTE_320x200x256_Color_28: db 0x2D,0x2D,0x2D
  PALETTE_320x200x256_Color_29: db 0x32,0x32,0x32
  PALETTE_320x200x256_Color_30: db 0x38,0x38,0x38
  PALETTE_320x200x256_Color_31: db 0x3F,0x3F,0x3F
  PALETTE_320x200x256_Color_32: db 0x0,0x0,0x3F
  PALETTE_320x200x256_Color_33: db 0x10,0x0,0x3F
  PALETTE_320x200x256_Color_34: db 0x1F,0x0,0x3F
  PALETTE_320x200x256_Color_35: db 0x2F,0x0,0x3F
  PALETTE_320x200x256_Color_36: db 0x3F,0x0,0x3F
  PALETTE_320x200x256_Color_37: db 0x3F,0x0,0x2F
  PALETTE_320x200x256_Color_38: db 0x3F,0x0,0x1F
  PALETTE_320x200x256_Color_39: db 0x3F,0x0,0x10
  PALETTE_320x200x256_Color_40: db 0x3F,0x0,0x0
  PALETTE_320x200x256_Color_41: db 0x3F,0x10,0x0
  PALETTE_320x200x256_Color_42: db 0x3F,0x1F,0x0
  PALETTE_320x200x256_Color_43: db 0x3F,0x2F,0x0
  PALETTE_320x200x256_Color_44: db 0x3F,0x3F,0x0
  PALETTE_320x200x256_Color_45: db 0x2F,0x3F,0x0
  PALETTE_320x200x256_Color_46: db 0x1F,0x3F,0x0
  PALETTE_320x200x256_Color_47: db 0x10,0x3F,0x0
  PALETTE_320x200x256_Color_48: db 0x0,0x3F,0x0
  PALETTE_320x200x256_Color_49: db 0x0,0x3F,0x10
  PALETTE_320x200x256_Color_50: db 0x0,0x3F,0x1F
  PALETTE_320x200x256_Color_51: db 0x0,0x3F,0x2F
  PALETTE_320x200x256_Color_52: db 0x0,0x3F,0x3F
  PALETTE_320x200x256_Color_53: db 0x0,0x2F,0x3F
  PALETTE_320x200x256_Color_54: db 0x0,0x1F,0x3F
  PALETTE_320x200x256_Color_55: db 0x0,0x10,0x3F
  PALETTE_320x200x256_Color_56: db 0x1F,0x1F,0x3F
  PALETTE_320x200x256_Color_57: db 0x27,0x1F,0x3F
  PALETTE_320x200x256_Color_58: db 0x2F,0x1F,0x3F
  PALETTE_320x200x256_Color_59: db 0x37,0x1F,0x3F
  PALETTE_320x200x256_Color_60: db 0x3F,0x1F,0x3F
  PALETTE_320x200x256_Color_61: db 0x3F,0x1F,0x37
  PALETTE_320x200x256_Color_62: db 0x3F,0x1F,0x2F
  PALETTE_320x200x256_Color_63: db 0x3F,0x1F,0x27
  PALETTE_320x200x256_Color_64: db 0x3F,0x1F,0x1F
  PALETTE_320x200x256_Color_65: db 0x3F,0x27,0x1F
  PALETTE_320x200x256_Color_66: db 0x3F,0x2F,0x1F
  PALETTE_320x200x256_Color_67: db 0x3F,0x37,0x1F
  PALETTE_320x200x256_Color_68: db 0x3F,0x3F,0x1F
  PALETTE_320x200x256_Color_69: db 0x37,0x3F,0x1F
  PALETTE_320x200x256_Color_70: db 0x2F,0x3F,0x1F
  PALETTE_320x200x256_Color_71: db 0x27,0x3F,0x1F
  PALETTE_320x200x256_Color_72: db 0x1F,0x3F,0x1F
  PALETTE_320x200x256_Color_73: db 0x1F,0x3F,0x27
  PALETTE_320x200x256_Color_74: db 0x1F,0x3F,0x2F
  PALETTE_320x200x256_Color_75: db 0x1F,0x3F,0x37
  PALETTE_320x200x256_Color_76: db 0x1F,0x3F,0x3F
  PALETTE_320x200x256_Color_77: db 0x1F,0x37,0x3F
  PALETTE_320x200x256_Color_78: db 0x1F,0x2F,0x3F
  PALETTE_320x200x256_Color_79: db 0x1F,0x27,0x3F
  PALETTE_320x200x256_Color_80: db 0x2D,0x2D,0x3F
  PALETTE_320x200x256_Color_81: db 0x31,0x2D,0x3F
  PALETTE_320x200x256_Color_82: db 0x36,0x2D,0x3F
  PALETTE_320x200x256_Color_83: db 0x3A,0x2D,0x3F
  PALETTE_320x200x256_Color_84: db 0x3F,0x2D,0x3F
  PALETTE_320x200x256_Color_85: db 0x3F,0x2D,0x3A
  PALETTE_320x200x256_Color_86: db 0x3F,0x2D,0x36
  PALETTE_320x200x256_Color_87: db 0x3F,0x2D,0x31
  PALETTE_320x200x256_Color_88: db 0x3F,0x2D,0x2D
  PALETTE_320x200x256_Color_89: db 0x3F,0x31,0x2D
  PALETTE_320x200x256_Color_90: db 0x3F,0x36,0x2D
  PALETTE_320x200x256_Color_91: db 0x3F,0x3A,0x2D
  PALETTE_320x200x256_Color_92: db 0x3F,0x3F,0x2D
  PALETTE_320x200x256_Color_93: db 0x3A,0x3F,0x2D
  PALETTE_320x200x256_Color_94: db 0x36,0x3F,0x2D
  PALETTE_320x200x256_Color_95: db 0x31,0x3F,0x2D
  PALETTE_320x200x256_Color_96: db 0x2D,0x3F,0x2D
  PALETTE_320x200x256_Color_97: db 0x2D,0x3F,0x31
  PALETTE_320x200x256_Color_98: db 0x2D,0x3F,0x36
  PALETTE_320x200x256_Color_99: db 0x2D,0x3F,0x3A
  PALETTE_320x200x256_Color_100: db 0x2D,0x3F,0x3F
  PALETTE_320x200x256_Color_101: db 0x2D,0x3A,0x3F
  PALETTE_320x200x256_Color_102: db 0x2D,0x36,0x3F
  PALETTE_320x200x256_Color_103: db 0x2D,0x31,0x3F
  PALETTE_320x200x256_Color_104: db 0x0,0x0,0x1C
  PALETTE_320x200x256_Color_105: db 0x7,0x0,0x1C
  PALETTE_320x200x256_Color_106: db 0xE,0x0,0x1C
  PALETTE_320x200x256_Color_107: db 0x15,0x0,0x1C
  PALETTE_320x200x256_Color_108: db 0x1C,0x0,0x1C
  PALETTE_320x200x256_Color_109: db 0x1C,0x0,0x15
  PALETTE_320x200x256_Color_110: db 0x1C,0x0,0xE
  PALETTE_320x200x256_Color_111: db 0x1C,0x0,0x7
  PALETTE_320x200x256_Color_112: db 0x1C,0x0,0x0
  PALETTE_320x200x256_Color_113: db 0x1C,0x7,0x0
  PALETTE_320x200x256_Color_114: db 0x1C,0xE,0x0
  PALETTE_320x200x256_Color_115: db 0x1C,0x15,0x0
  PALETTE_320x200x256_Color_116: db 0x1C,0x1C,0x0
  PALETTE_320x200x256_Color_117: db 0x15,0x1C,0x0
  PALETTE_320x200x256_Color_118: db 0xE,0x1C,0x0
  PALETTE_320x200x256_Color_119: db 0x7,0x1C,0x0
  PALETTE_320x200x256_Color_120: db 0x0,0x1C,0x0
  PALETTE_320x200x256_Color_121: db 0x0,0x1C,0x7
  PALETTE_320x200x256_Color_122: db 0x0,0x1C,0xE
  PALETTE_320x200x256_Color_123: db 0x0,0x1C,0x15
  PALETTE_320x200x256_Color_124: db 0x0,0x1C,0x1C
  PALETTE_320x200x256_Color_125: db 0x0,0x15,0x1C
  PALETTE_320x200x256_Color_126: db 0x0,0xE,0x1C
  PALETTE_320x200x256_Color_127: db 0x0,0x7,0x1C
  PALETTE_320x200x256_Color_128: db 0xE,0xE,0x1C
  PALETTE_320x200x256_Color_129: db 0x11,0xE,0x1C
  PALETTE_320x200x256_Color_130: db 0x15,0xE,0x1C
  PALETTE_320x200x256_Color_131: db 0x18,0xE,0x1C
  PALETTE_320x200x256_Color_132: db 0x1C,0xE,0x1C
  PALETTE_320x200x256_Color_133: db 0x1C,0xE,0x18
  PALETTE_320x200x256_Color_134: db 0x1C,0xE,0x15
  PALETTE_320x200x256_Color_135: db 0x1C,0xE,0x11
  PALETTE_320x200x256_Color_136: db 0x1C,0xE,0xE
  PALETTE_320x200x256_Color_137: db 0x1C,0x11,0xE
  PALETTE_320x200x256_Color_138: db 0x1C,0x15,0xE
  PALETTE_320x200x256_Color_139: db 0x1C,0x18,0xE
  PALETTE_320x200x256_Color_140: db 0x1C,0x1C,0xE
  PALETTE_320x200x256_Color_141: db 0x18,0x1C,0xE
  PALETTE_320x200x256_Color_142: db 0x15,0x1C,0xE
  PALETTE_320x200x256_Color_143: db 0x11,0x1C,0xE
  PALETTE_320x200x256_Color_144: db 0xE,0x1C,0xE
  PALETTE_320x200x256_Color_145: db 0xE,0x1C,0x11
  PALETTE_320x200x256_Color_146: db 0xE,0x1C,0x15
  PALETTE_320x200x256_Color_147: db 0xE,0x1C,0x18
  PALETTE_320x200x256_Color_148: db 0xE,0x1C,0x1C
  PALETTE_320x200x256_Color_149: db 0xE,0x18,0x1C
  PALETTE_320x200x256_Color_150: db 0xE,0x15,0x1C
  PALETTE_320x200x256_Color_151: db 0xE,0x11,0x1C
  PALETTE_320x200x256_Color_152: db 0x14,0x14,0x1C
  PALETTE_320x200x256_Color_153: db 0x16,0x14,0x1C
  PALETTE_320x200x256_Color_154: db 0x18,0x14,0x1C
  PALETTE_320x200x256_Color_155: db 0x1A,0x14,0x1C
  PALETTE_320x200x256_Color_156: db 0x1C,0x14,0x1C
  PALETTE_320x200x256_Color_157: db 0x1C,0x14,0x1A
  PALETTE_320x200x256_Color_158: db 0x1C,0x14,0x18
  PALETTE_320x200x256_Color_159: db 0x1C,0x14,0x16
  PALETTE_320x200x256_Color_160: db 0x1C,0x14,0x14
  PALETTE_320x200x256_Color_161: db 0x1C,0x16,0x14
  PALETTE_320x200x256_Color_162: db 0x1C,0x18,0x14
  PALETTE_320x200x256_Color_163: db 0x1C,0x1A,0x14
  PALETTE_320x200x256_Color_164: db 0x1C,0x1C,0x14
  PALETTE_320x200x256_Color_165: db 0x1A,0x1C,0x14
  PALETTE_320x200x256_Color_166: db 0x18,0x1C,0x14
  PALETTE_320x200x256_Color_167: db 0x16,0x1C,0x14
  PALETTE_320x200x256_Color_168: db 0x14,0x1C,0x14
  PALETTE_320x200x256_Color_169: db 0x14,0x1C,0x16
  PALETTE_320x200x256_Color_170: db 0x14,0x1C,0x18
  PALETTE_320x200x256_Color_171: db 0x14,0x1C,0x1A
  PALETTE_320x200x256_Color_172: db 0x14,0x1C,0x1C
  PALETTE_320x200x256_Color_173: db 0x14,0x1A,0x1C
  PALETTE_320x200x256_Color_174: db 0x14,0x18,0x1C
  PALETTE_320x200x256_Color_175: db 0x14,0x16,0x1C
  PALETTE_320x200x256_Color_176: db 0x0,0x0,0x10
  PALETTE_320x200x256_Color_177: db 0x4,0x0,0x10
  PALETTE_320x200x256_Color_178: db 0x8,0x0,0x10
  PALETTE_320x200x256_Color_179: db 0xC,0x0,0x10
  PALETTE_320x200x256_Color_180: db 0x10,0x0,0x10
  PALETTE_320x200x256_Color_181: db 0x10,0x0,0xC
  PALETTE_320x200x256_Color_182: db 0x10,0x0,0x8
  PALETTE_320x200x256_Color_183: db 0x10,0x0,0x4
  PALETTE_320x200x256_Color_184: db 0x10,0x0,0x0
  PALETTE_320x200x256_Color_185: db 0x10,0x4,0x0
  PALETTE_320x200x256_Color_186: db 0x10,0x8,0x0
  PALETTE_320x200x256_Color_187: db 0x10,0xC,0x0
  PALETTE_320x200x256_Color_188: db 0x10,0x10,0x0
  PALETTE_320x200x256_Color_189: db 0xC,0x10,0x0
  PALETTE_320x200x256_Color_190: db 0x8,0x10,0x0
  PALETTE_320x200x256_Color_191: db 0x4,0x10,0x0
  PALETTE_320x200x256_Color_192: db 0x0,0x10,0x0
  PALETTE_320x200x256_Color_193: db 0x0,0x10,0x4
  PALETTE_320x200x256_Color_194: db 0x0,0x10,0x8
  PALETTE_320x200x256_Color_195: db 0x0,0x10,0xC
  PALETTE_320x200x256_Color_196: db 0x0,0x10,0x10
  PALETTE_320x200x256_Color_197: db 0x0,0xC,0x10
  PALETTE_320x200x256_Color_198: db 0x0,0x8,0x10
  PALETTE_320x200x256_Color_199: db 0x0,0x4,0x10
  PALETTE_320x200x256_Color_200: db 0x8,0x8,0x10
  PALETTE_320x200x256_Color_201: db 0xA,0x8,0x10
  PALETTE_320x200x256_Color_202: db 0xC,0x8,0x10
  PALETTE_320x200x256_Color_203: db 0xE,0x8,0x10
  PALETTE_320x200x256_Color_204: db 0x10,0x8,0x10
  PALETTE_320x200x256_Color_205: db 0x10,0x8,0xE
  PALETTE_320x200x256_Color_206: db 0x10,0x8,0xC
  PALETTE_320x200x256_Color_207: db 0x10,0x8,0xA
  PALETTE_320x200x256_Color_208: db 0x10,0x8,0x8
  PALETTE_320x200x256_Color_209: db 0x10,0xA,0x8
  PALETTE_320x200x256_Color_210: db 0x10,0xC,0x8
  PALETTE_320x200x256_Color_211: db 0x10,0xE,0x8
  PALETTE_320x200x256_Color_212: db 0x10,0x10,0x8
  PALETTE_320x200x256_Color_213: db 0xE,0x10,0x8
  PALETTE_320x200x256_Color_214: db 0xC,0x10,0x8
  PALETTE_320x200x256_Color_215: db 0xA,0x10,0x8
  PALETTE_320x200x256_Color_216: db 0x8,0x10,0x8
  PALETTE_320x200x256_Color_217: db 0x8,0x10,0xA
  PALETTE_320x200x256_Color_218: db 0x8,0x10,0xC
  PALETTE_320x200x256_Color_219: db 0x8,0x10,0xE
  PALETTE_320x200x256_Color_220: db 0x8,0x10,0x10
  PALETTE_320x200x256_Color_221: db 0x8,0xE,0x10
  PALETTE_320x200x256_Color_222: db 0x8,0xC,0x10
  PALETTE_320x200x256_Color_223: db 0x8,0xA,0x10
  PALETTE_320x200x256_Color_224: db 0xB,0xB,0x10
  PALETTE_320x200x256_Color_225: db 0xC,0xB,0x10
  PALETTE_320x200x256_Color_226: db 0xD,0xB,0x10
  PALETTE_320x200x256_Color_227: db 0xF,0xB,0x10
  PALETTE_320x200x256_Color_228: db 0x10,0xB,0x10
  PALETTE_320x200x256_Color_229: db 0x10,0xB,0xF
  PALETTE_320x200x256_Color_230: db 0x10,0xB,0xD
  PALETTE_320x200x256_Color_231: db 0x10,0xB,0xC
  PALETTE_320x200x256_Color_232: db 0x10,0xB,0xB
  PALETTE_320x200x256_Color_233: db 0x10,0xC,0xB
  PALETTE_320x200x256_Color_234: db 0x10,0xD,0xB
  PALETTE_320x200x256_Color_235: db 0x10,0xF,0xB
  PALETTE_320x200x256_Color_236: db 0x10,0x10,0xB
  PALETTE_320x200x256_Color_237: db 0xF,0x10,0xB
  PALETTE_320x200x256_Color_238: db 0xD,0x10,0xB
  PALETTE_320x200x256_Color_239: db 0xC,0x10,0xB
  PALETTE_320x200x256_Color_240: db 0xB,0x10,0xB
  PALETTE_320x200x256_Color_241: db 0xB,0x10,0xC
  PALETTE_320x200x256_Color_242: db 0xB,0x10,0xD
  PALETTE_320x200x256_Color_243: db 0xB,0x10,0xF
  PALETTE_320x200x256_Color_244: db 0xB,0x10,0x10
  PALETTE_320x200x256_Color_245: db 0xB,0xF,0x10
  PALETTE_320x200x256_Color_246: db 0xB,0xD,0x10
  PALETTE_320x200x256_Color_247: db 0xB,0xC,0x10
  PALETTE_320x200x256_Color_248: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_249: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_250: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_251: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_252: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_253: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_254: db 0x0,0x0,0x0
  PALETTE_320x200x256_Color_255: db 0x0,0x0,0x0


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Register Values for Mode 13h (Default text font)

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Default Text Font, Mode 13h, Graphics, 320x200x256 Colors, MCGA

This is a graphics mode so it doesn't use text fonts.

Instead you'll need direct drawing techniques along with the default font to get text with your own routines. We don't provide it here (it would be part of a drawing tutorial).

Anyway, in this mode we would effectively get a text area with an 40x12x256 colors resolution implemented in software.
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