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Hey all, the Visopsys guy here.

I've finally gotten around to adding SMP to my kernel. A major problem I've encountered with my architecture is: application processors seem unable to do old-fashioned x86 port I/O to legacy devices that require it.

I've done some searching here and on the wider web, and come up empty-handed (perhaps my search terms weren't good enough to cut through all the chaff). I've tried working around it with a daemon-style process running on the boot processor, calling a special driver to do the I/O, but it's been unwieldy and so far not very successful.

What I'm wondering is: is there a way to map this stuff into an application processor's memory space? I confess I'm not too adept with the legacy hardware side of things - knowing how the old-fashioned ISA I/O bus works, how the processors are connected to it, etc.

APs can access legacy I/O ports exactly the same as the BSP. Something else must be causing the problem you're seeing.

Worth looking at this - https://www.intel.com.tw/content/dam/ww ... asheet.pdf

That covers how 10th Generation Intel Core processors handle I/O. They're converted to DMI accesses.

Basically, there's no reason that it wouldn't work from an AP. However, chipsets are complicated. It's worth trying to get the manual for your specific hardware configuration.

Thank you both. Your replies got me thinking about it more broadly, and I realized it's probably the way I'm handling the interrupts