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I'm currently developing an OS for x86_64. The PIT has been registered through the IOAPIC (GSI 0, IDT vector 34). When the TSC calls it, it uses one-shot mode with a 30ms timeout. The PIC has been masked, and the PIT has also registered the IDT vector and set up a callback.

During debugging, I set the PIT to mode 2 with an initial value and looped to print the PIT counter. The values decreased gradually, so the PIT counter appears to be working. I also tried changing the polarity when registering with the IOAPIC, but it didn't help. I added another debug check: after writing to the IOAPIC, the PIT initialization code verifies the written values and prints them – they are all correct.

However, for some reason, the interrupt just won't fire. Currently, IPI-triggered interrupts work fine.

My GitHub repository: https://github.com/shizi297/ShiziOS
Tag: pit-bug
Tagged repository link: https://github.com/shizi297/ShiziOS/tree/pit-bug

I'm using QEMU, with the specific configuration in the "run" target of the root CMakeLists.txt file.

Are you sure that PIT is connected to GSI 0? It is almost everywhere connected to GSI 2.

Thank you for your reply! I previously assumed that the PIT was connected to GSI 0, because in my understanding, ISA IRQ0 should map directly to GSI 0 (my IOAPIC base starts at 0). But your hint made me question this assumption. In fact, I just tried registering it as GSI 2, and it worked.

shizi wrote: ↑Tue Feb 24, 2026 9:52 pmin my understanding, ISA IRQ0 should map directly to GSI 0

You have to check the MADT for interrupt source overrides. ISA IRQs map directly to GSIs by default, but there is usually an override for ISA IRQ0 to map it to GSI 2.