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Intel wrote: These registers are accessed via I/O space. The I/O space resides in the PCI compatibility hole and uses only the addresses that were part of the original VGA I/O space (which includes EGA and MDA emulation). Accesses to the VGA I/O addresses are steered to the proper bus and rely on proper setup of bridge registers. Extended VGA registers such as GR10 and GR11 use additional indexes for the already defined I/O addresses. VGA register accesses are allowed as 8 or 16 bit naturally aligned transactions only. Word transactions must have the least significant bit of the address set to zero. DWORD I/O operations should not be performed on these registers.

Some products may support access to these registers through MMIO. The access method varies and is documented elsewhere.

thorfdbg wrote: ↑Mon Dec 01, 2025 6:56 am All fine, but from this follows that the Bios (or the Os, for that matter) *cannot* configure more than one VGA compatible display device as otherwise more than one device would potentially listen to the legacy VGA registers. Does that mean that a PCI bus scan has to be refined in such sense that the device class needs to be checked, and if the class is a VGA compatible display device, the bios needs to check whether this is the only device of such type and if not so, refuse to configure it?

thorfdbg wrote: ↑Mon Dec 01, 2025 9:28 am This is not about BARs at all, and that is precisely the issue. A VGA device reacts on the legacy IO space, no matter where its bars are mapped. If a VGA device can be programmed (and woken up) through one of the BAR areas, and keeps itself out of the legacy IO space after being configured, that is just wonderful. Unfortunately, not all devices are that way, and the way how the (legacy) Bios works they cannot be - to my understanding. VGA devices need to react on the CRTC, SEQ and CRTC ports, no matter how the BARs are mapped, but potentially have these registers replicated somewhere in the MMIO area (or are programmed there by completely different means, but then by an Os device driver).

The issue is that the Bios needs to be able to get a configuration dialog on the screen, and the only thing a Bios (not UEFI) can depend upon for that is the legacy VGA area - without any BARs anywhere.

Hence, the question, if the bios wakes up a VGA device by writing 1 to port 0x3c3, how does it know which graphics card will respond, given that two or more of them are in the system? So, how does bootstrapping and the Bios works in the presence of multiple cards?

thorfdbg wrote: ↑Mon Dec 01, 2025 1:57 pm Ok, so this means that the Bios needs to turn off the IO space of all VGA like devices, except the selected one, then work from this device.

thorfdbg wrote: ↑Tue Dec 02, 2025 5:15 am UEFI is another story. That's a graphical screen, but I was really talking about "plain old bios", and from what I see, I would expect that this is a text mode and that would work through the VGA legacy register set. Sure, one would consider that it is configured through the boot ROM of the card, but that opens up just a follow-up question: How is that ROM mapped? For PCI, it is the ROM configuration space, but is the Bios already using that? Or instead, the VESA bios at c000:0000? And finally, who maps the VESA Bios there and how?

if (rom_header) {
		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
		       dev_path(dev), rom_header);
	} else if (CONFIG(ON_DEVICE_ROM_LOAD)) {
		uintptr_t rom_address;

		rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);

		if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
			if (CONFIG(CPU_QEMU_X86) && (dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
				rom_address = 0xc0000;
			else
				return NULL;
		} else {
			/* Enable expansion ROM address decoding. */
			pci_write_config32(dev, PCI_ROM_ADDRESS,
					   rom_address|PCI_ROM_ADDRESS_ENABLE);
		}

		rom_address &= PCI_ROM_ADDRESS_MASK;

		printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n",
		       dev_path(dev), (unsigned long)rom_address);
		rom_header = (struct rom_header *)rom_address;
	} else {
		printk(BIOS_DEBUG, "PCI Option ROM loading disabled for %s\n",
		       dev_path(dev));
		return NULL;
	}