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The other day, I accidentally left out the code to save and restore DS, ES, etc from an interrupt service routine. Imagine my surprise when the ISR still functioned as normal - no faults at all. This is despite accessing memory marked "supervisor" in the page tables, and despite running privilleged instructions like INVLPG

From what I can understand of the latest Intel manual, this is normal: "When the CPL is 0, data segments at all privillege levels are accessible" - section 6.6 of the Intel Software Developer Manuals Volume 3 (2025)

All of this causes me to question: in a flat memory model, are seperate data segments truly needed for both ring0 and ring3? Is the processor actually checking or using the privillege level of these segment descriptors at any point?

I understand that for thread-local storage etc it's useful to save and reload FS or GS - but appart from that, is loading ring0 data segment selectors into the relevant registers actually doing anything useful?

Thanks for your help

InvalidOpcode wrote: ↑Tue Aug 12, 2025 4:15 pmAll of this causes me to question: in a flat memory model, are seperate data segments truly needed for both ring0 and ring3? Is the processor actually checking or using the privillege level of these segment descriptors at any point?

You need a ring 0 data segment for the SS register. The processor won't allow you to use your ring 3 data segment for the ring 0 stack.

InvalidOpcode wrote: ↑Tue Aug 12, 2025 4:15 pmI understand that for thread-local storage etc it's useful to save and reload FS or GS - but appart from that, is loading ring0 data segment selectors into the relevant registers actually doing anything useful?

I'm not sure if they need to be ring 0 data segments specifically, but they do need to be valid data segments. There's nothing stopping code running in ring 3 from loading a code segment or a null segment into DS instead of a data segment.

Thankyou for explaining! This helps

Looks like I can use a few less instructions than I was expecting, by loading a default value into es, ds rather than saving and restoring in each ISR, and using the same segment in es & ds for both usermode and in the kernel (but keeping a ring0 stack segment and ensuring es & ds are correct on ISR entry)