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Hello Octocontrabass/anyone

can you please point to me the right driver used by Linux for Ethernet(Intel EHL SGMII -> pHY) and any to the point reference implementation or documents, it will help me lot

currently i am looking in "https://elixir.bootlin.com/linux/v6.10. ... rnet/intel", to find the right driver

Thanks
Ravi

All three Ethernet devices are handled by this driver.

Hello Octocontrabass

Last couple of days i was trying to understand the fabric of ETHERNET implementation, i will think it will take some time for me to get up there..

But i wanted to test something,

when the board boots up via slimboot and uefi, the ethernet interface is already configured,,,keeping this in mind my question can i transmit any test data by directly writing into Tx buffer or something, i am trying to find the register in data sheet

Thanks
Ravi

If the ethernet controller is already configured and enabled, you should be able to transmit data by writing to the descriptor list and updating the DMA tail pointer.

But that assumes everything is configured. It might not be that easy.

Hello Octocontrabass is it possible to do without DMA

Does EHL use Synopsys DWMAC, if yes when i check the block diagrams in STM controller,, it appears it is not possible

https://www.st.com/resource/en/referenc ... ronics.pdf

Page 3063,, i know its only RGMII in the above STM, but i assume its similar to EHL

is this the right file where data transfer happens ?https://github.com/torvalds/linux/blob/ ... mac_main.c

ravi wrote: ↑Wed Sep 11, 2024 6:49 amis it possible to do without DMA

I didn't see any way to access the Tx FIFO without DMA.

ravi wrote: ↑Wed Sep 11, 2024 6:49 amDoes EHL use Synopsys DWMAC

Linux says EHL uses a variant of DWMAC4.

ravi wrote: ↑Wed Sep 11, 2024 6:49 amis this the right file where data transfer happens ?https://github.com/torvalds/linux/blob/ ... mac_main.c

That's the main driver, but it calls different functions for different Synopsys hardware, so data transfer probably happens in a different file.

Octocontrabass wrote: ↑Tue Sep 10, 2024 3:45 pm If the ethernet controller is already configured and enabled, you should be able to transmit data by writing to the descriptor list and updating the DMA tail pointer.

But that assumes everything is configured. It might not be that easy.

Hi Octocontrabass, is it possible for you to give me some more details about this

let me know if you are aware of, where the current interface mac and IP address is stored, i think i scanned the relevant registers(as per my understanding) did not find the information, is this something transferred to PHY during init, and then on PHY is responsible

Thanks
Ravi

ravi wrote: ↑Sat Sep 14, 2024 2:57 pmlet me know if you are aware of, where the current interface mac and IP address is stored

The current MAC address should be stored in MAC_ADDRESS0_HIGH and MAC_ADDRESS0_LOW.

The current IP address might not be stored anywhere. If the firmware chose to enable layer 3 packet filtering, the current IPv4 address might be stored in MAC_LAYER3_ADDR1_REG0 or MAC_LAYER3_ADDR1_REG1. (IPv6 uses all four of MAC_LAYER3_ADDRx_REG0 or all four of MAC_LAYER3_ADDRx_REG1.) You might have better luck using UEFI boot services to ask the firmware for the current IP address.

Are you sure the firmware assigned an IP address?

Yeah, working on it

i think MAC address was showing all 0's in ip config command that's why all the MAC address registers(0 to 64) where 0's is my guess


Thanks
Ravi

Hello Octocontrabass ,

i am slowly understanding the DMA Desc and how things are transmitted, but i did not get how form where the Destination MAC address is obtained(which register or something)

Thanks
Ravi

The destination MAC address won't be in any register. You can use ARP (IPv4) or NDP (IPv6) to find it, or you can try asking the firmware using UEFI boot services.

Hello Octocontrabass

i have the MAC address say "11, 22, 33, 44, 55, 66"

how do i provide this information to the MAC, to insert it in its frame


Thanks
Ravi

The MAC can't insert the destination MAC address, only the source MAC address. You have to put the destination MAC address in the frames you send.

The Intel EHL Ethernet hardware is i2xx. It seems to be a rather robust design and doesn't require a huge amount of patches as today's RTL hardware. It's my favorite Ethernet hardware at the moment, and I always make sure new hardware I buy has this and not Realtek.

You should setup the hardware and initialize the in-memory schedules yourself. It's not very complicated if you can handle PCIe. It's also well documented.

rdos wrote: ↑Tue Sep 24, 2024 12:58 amThe Intel EHL Ethernet hardware is i2xx.

According to the Elkhart Lake datasheets, the SoC Ethernet hardware is Synopsys DWMAC4. Where are you seeing i2xx?