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hello Octocontrabass

i want to use HPET timer 0, but my CPU operates in 32 bit mode so is this possible

i am asking because if i switch the HPET to 32 bit mode, master counter will over flow every few seconds, so i will have to track it update my comparator register, which takes time

if use it in 64 bit mode, i this there will some race conditions, since the CPU is 32 bit mode, it cannot access 64 bit Master counter and Comparator registers atomically i believe this is a problem do you agree?

How to get the FSB interrupts

HPET registers have FSB Interrupts Address and FSB interrupt values, i am little bit confused by values what is it

i have had set up for other interrupts using IOAPIC, i set the vector number in IOREDTABLE register at specified GSI number provided form the slim boot for a particular device

all the 255 or so vectors(intgate) and corresponding ISR address are defined

can you explain me if possible,,, in this context what should be interrupt address and what should be the value



FSB Address,,, a value i get form data sheet? or from where?
FSB value,,, a vector number?

The easiest way to read a consistent 64-bit timestamp if you only have 32-bit registers available is:

1. Read high part.
2. Read low part.
3. Read high part again. If it changed since step 1, return to step 1.

Easy enough to do with a three line loop. For writing the comparators, easiest would be to disable the timer during the operation. Alternatively, you could do something like

1. Set high part to 0xffffffff
2. Set low part
3. Set high part

This makes spurious interrupts as unlikely as possible, since the intermediate values written are far in the future.

Hello nullplan

thanks for your response:

1) what i intended to ask was, in periodic mode processor has to do reads and writes by itself, so will it do right?...

2) what about FSB address and FSB value?


Thanks
Ravi

ravi wrote: ↑Tue Aug 27, 2024 1:23 pmsince the CPU is 32 bit mode, it cannot access 64 bit Master counter and Comparator registers atomically

You can use x87 or SSE instructions (FILD/FISTP/MOVQ) for atomic 64-bit reads and writes.

ravi wrote: ↑Tue Aug 27, 2024 1:51 pmwhat about FSB address and FSB value?

Those are for message-signaled interrupts. They're documented in the Intel SDM volume 3A section 11.11, Message Signalled Interrupts.

Hello Octocontrabass,

Got HPET working, working on HPET-interrupts now

Thanks
Ravi

got it

Hello Octocontrabass,

i was able to get the interrupts form IOAPIC-APIC but not from FSB(MSI)

1) i enabled FSB intr in HPET timer 0 config
2) Set FSB Address to 0xFEE00000(even tried with all the APIC Id's)
3) Set FSB value as 0x148, (low priority and vector= 72)


i checked the UEFI memory dump, i think it uses HPET 0 is FSB interrupt mode, but in one shot mode not periodic,, its the same as above

but still i am not able to get interrupt,,,, is there any additional thing , i have missed to enable MSI interrupts

Note: CPU is 32 bit protected mode(no paging, paging is disabled)

Thanks
Ravi

ravi wrote: ↑Thu Aug 29, 2024 8:01 pm3) Set FSB value as 0x148, (low priority and vector= 72)

Try 0x48.

ravi wrote: ↑Thu Aug 29, 2024 8:01 pmis there any additional thing , i have missed to enable MSI interrupts

LEG_RT_CNF must be 0. TIMER0_INT_TYPE_CNF must be 0.

Hello Octocontrabass,

i had already disabled legacy interrupt routing(LEG_RT_CN) and set interrupts as edge triggered (TIMER0_INT_TYPE_CNF)


as you have suggested, i will try with 0x48

Thanks
Ravi