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HI

I am trying to get UART(which is PCI device, internal, intel Atom processor) as per the data sheet, this device interrupts by-passes IOAPIC and directly connected to APIC

so question how to setup the UART IRQ33 to specific vector address for the ISR

Thanks

I'd like to see that datasheet. Which Atom processor?

HI
i cannot post the data here(NDA), but the document is RDC-610273

Intel Atom-6000E series

thanks

but in principle if i want to get interrupts without IOAPIC

how do i do it

APIC documentation shows LVT's for only few thing like Timer.. etc if i want for UART 1 and 2 etc. how do i do it

thanks

Everything I can find says the UART IRQs are ordinary PCI IRQs that get delivered to the IOxAPIC, same as any other PCI IRQ. The PSE UARTs support MSI, which you can use to deliver interrupts directly to the local APIC instead of using the IOxAPIC. The SIO UARTs don't appear to support MSI.

Where exactly does that document say UART IRQs bypass the IOxAPIC?

hi Thanks

Page 47 if you can see the diagram(path for Dev25)

Thanks

to give some context to my problem

i am using slim boot loader on Elkhart lake platform, slim boot loader configures UART 2 to IRQ 33(i think this is GSI) and IntC

i wanted to get UART tx interrupts(when the buffer is empty)

1) so i configured the IO-APIC entry with for IRQ 33 to trigger a interrupt 0x27 in my IDT and set the UART IER to 02 (interrupt of tx buffer empty)(and also no FIFO )

2) when i transmit a character, i will hit the ISR, but when i check the IIR it say 01 , indicating no interrupt pending, it appears that its hitting ISR when buffer is not empty

note: i have observed other anomalies also

1) IIR is set 1 or 2 times when i transmit 4 characters(when in edge trigger mode in IOAPIC), bit PCIE command status registers (pci config space)show 4 times interrupts have occurred
2) when i configure to level trigger IO APIC i get uncontrolled number of interrupts continuously

thanks

The diagram doesn't make sense. It looks like someone was editing it and moved the IOAPIC box without moving all of the attached arrows.

ravi wrote:i am using slim boot loader on Elkhart lake platform, slim boot loader configures UART 2 to IRQ 33(i think this is GSI) and IntC

How are you getting those values?

https://github.com/slimbootloader/slimb ... ree.asl#L9

Dev 25 function 2

// D25
Package(){0x0019FFFF, 0, 0, 31 },
Package(){0x0019FFFF, 1, 0, 32 },
Package(){0x0019FFFF, 2, 0, 33 },

Where did you get INTC? That table says any function on device 25 that uses INTC will be routed to GSI 33, but it doesn't say which function uses INTC.

Did you use the _PIC method to switch to APIC mode?

The snippet he quoted is from AR00, which is what _PRT returns in APIC mode. To me it looks like an error, because the MADT only defines a single IOAPIC, and seems to think it has 24 pins. Meaning only GSI 0-23 are allowed. Even if it did have 32 lines, that means all GSI numbers from 32 onward are bad, but given in AR00 constantly, anyway. I'm not sure how to proceed. My OS would probably fail initialization of the device under these circumstances.

Hi
https://github.com/slimbootloader/slimb ... Lib.c#L170
{25, 2, SiPchIntC, 33}, // SerialIo UART Controller #2, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[9]

i have not not called _PIC method and i am under assumption that slimboot loader sets it up in APIC mode(the reason, i did the same with timer->IOAPIC->APIC->CPU, i am getting the timer interrupts at the right intervals )

"and seems to think it has 24 pins. Meaning only GSI 0-23 are allowed", as per knowledge , it does't need to be one to one mapping between IOAPIC pins and GSI numbers, GSI numbers are flat remapping of 0-255, let me know if my understanding is correct.

i think something is lacking in my approach, interrupts is happening when a character is sent , out 4 time only one or 2 times i get 02 in IIR(i.e transmit buffer empty)

thanks
Ravi

ravi wrote:as per knowledge , it does't need to be one to one mapping between IOAPIC pins and GSI numbers, GSI numbers are flat remapping of 0-255, let me know if my understanding is correct.

It is my understanding that the correspondence between GSI numbers and IOAPIC pin numbers is defined in the MADT. The MADT defines which IOAPICs exist and what their GSI base is. But for your platform, the MADT only defines a single IOAPIC with a GSI base of 0, so only GSI 0-23 are even valid on your platform. It doesn't make sense to refer to GSI 31 because you don't even know what interrupt controller controls that GSI. The LAPIC LINT lines cannot be referred to in this way, and nor can MSI numbers.

If you wish to learn more about this, you can look at the ACPI spec at https://uefi.org/specs/ACPI/6.5/05_ACPI ... interrupts.

ravi wrote:i think something is lacking in my approach, interrupts is happening when a character is sent , out 4 time only one or 2 times i get 02 in IIR(i.e transmit buffer empty)

OK, so which interrupt is happening?

nullplan wrote:To me it looks like an error, because the MADT only defines a single IOAPIC, and seems to think it has 24 pins.

The MADT doesn't specify how many IRQ pins are on the IOAPIC, that information comes from the IOAPIC itself. This IOAPIC has 120 pins.

ravi wrote:i have not not called _PIC method and i am under assumption that slimboot loader sets it up in APIC mode

According to the MADT, the default is PIC mode. You must call the _PIC method to switch to APIC mode.

thanks i will read it

i am not sure which interrupt is happing 100%

1) i have set only UART2 IER t 02 (i.e interrupt on empty)
2) when i see in the PCI header register(command and status registers ) for my UART(dev 25), i can see that its indicating that device is in interrupt state(its gets cleared when i read it)... this made me believe that UART is only interrupt (when i check IIR says 0x1, 3 out of 4 interrupts and one time it says 0x2 )
3) also interrupt occurs after i send a character, this also made me believe that UART is interrupting

Thanks
Ravi