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Hey all! In our PCI docs, https://wiki.osdev.org/PCI we have RAM (class 5, subclass 0) and Processors (class 0xB) listed as attachable devices. Does that mean one could get a PCI-to-CPU-socket or PCI-to-DDR adapter? I checked online and i couldn't find anything of that sort...

Thanks in advance!

jaihsonk wrote:Hey all! In our PCI docs, https://wiki.osdev.org/PCI we have RAM (class 5, subclass 0) and Processors (class 0xB) listed as attachable devices. Does that mean one could get a PCI-to-CPU-socket or PCI-to-DDR adapter? I checked online and i couldn't find anything of that sort...

Thanks in advance!

Yes, CPUs can be attatched by PCI. For a real world example, https://en.wikipedia.org/wiki/Xeon_Phi, or of course GPUs, although they show as a graphics card.

But as far as I can tell, this is used in the world of asymmetric coprocessing. Coprocessing was newfangled when PCI came in, so it was natural to try and design in some forward compatibility.

What about RAM?
Can I take out the regular CPU from my desktop, plug in the Xeon Phi (or another PCI CPU) and have that running by itself?
What should an OS do when it comes across a PCI CPU?

Also, Can a PCI CPU and a regular CPU run simultaneously? If so, would that be considered a supercomputer?

jaihsonk wrote:What about RAM?
Can I take out the regular CPU from my desktop, plug in the Xeon Phi (or another PCI CPU) and have that running by itself?

Probably not. PCs are designed to bootstrap using the main processor.

Some platforms do something similar though. The RaspberryPi, for example, is bootstrapped by the GPU, which then starts the "main" CPU(s) to run your OS. But this isn't the mainstream way of doing things, certainly on anything like a PC or similar machine.

But then this depends on where you draw the line. Some Intel chipsets contain a complete embedded computer, running a private copy of Minix OS, to run the Management Engine, completely seperately to the main CPU. I'm not sure if this Minix gets control before your main CPU is booted and is involved in booting the CPU, in a manner similar to the RPi.

This video might answer that (I've not watched it yet.)

jaihsonk wrote: What should an OS do when it comes across a PCI CPU?

Absent a specific example, it's hard to say, other than to ignore the PCI card if the OS doesn't have a driver for it.

jaihsonk wrote:What about RAM?

PCI is old enough that class 0x05 may have originally been intended for RAM expansion cards, but nowadays it's only used as a way to access the chipset's memory controller.

As far as I know, no PCI RAM expansion cards exist.

jaihsonk wrote:Can I take out the regular CPU from my desktop, plug in the Xeon Phi (or another PCI CPU) and have that running by itself?

No. A PCI CPU can't initialize the rest of the PC.

jaihsonk wrote:What should an OS do when it comes across a PCI CPU?

Ask the user to send you documentation so you can write a driver for it.

jaihsonk wrote:Also, Can a PCI CPU and a regular CPU run simultaneously?

Yes.

jaihsonk wrote:If so, would that be considered a supercomputer?

No. Regular PC CPUs are already made of multiple smaller CPUs stuck together, so adding one more doesn't make that big of a difference.

Octocontrabass wrote:

jaihsonk wrote:If so, would that be considered a supercomputer?

No. Regular PC CPUs are already made of multiple smaller CPUs stuck together, so adding one more doesn't make that big of a difference.

To be clear, a Xeon Phi can have 72 cores.

Consider a server board, the SUPERMICRO MBD-H8QG6+-F-O

That'll take 4x 16-core AMD Opteron 6300s, for a total of 64 cores. Now add a Xeon Phi, or two. That's a lot of cores!

But this is still not supercomputer territory, not these days.

OK I had the old definition of a supercomputer as being 2+ processors working off the same memory.
Thanks for your help

bellezzasolo wrote:

Octocontrabass wrote:

jaihsonk wrote:If so, would that be considered a supercomputer?

No. Regular PC CPUs are already made of multiple smaller CPUs stuck together, so adding one more doesn't make that big of a difference.

To be clear, a Xeon Phi can have 72 cores.

Consider a server board, the SUPERMICRO MBD-H8QG6+-F-O

That'll take 4x 16-core AMD Opteron 6300s, for a total of 64 cores. Now add a Xeon Phi, or two. That's a lot of cores!

But this is still not supercomputer territory, not these days.

I want a motherboard like that for experimentation.

When I actually researched for a new "super-computer", I looked at multi-socket motherboards, but in the end I concluded that the high cost didn't seem to correlate well with performance, so I built my system around a single 12-core AMD thread ripper CPU with 128 GB of memory instead.

I'm having a hard time understanding PCI. I'm not a fast learner and I'm not good with docs lol Does anyone have a good implementation I can study?

Which PCI slot does CONFIG_ADDRESS and CONFIG_DATA address/read from? Or am I talking to some PCI master controller?
Where can I read the PCI device structure from? Or is the structure composed of data from multiple ports?

Sorry if these are foolish questions, I understand things better when people and real examples (as opposed to documents) tell me how things work

jaihsonk wrote:Which PCI slot does CONFIG_ADDRESS and CONFIG_DATA address/read from? Or am I talking to some PCI master controller?

You're talking to "some PCI master controller" - it's called a PCI host bridge. You write an address to CONFIG_ADDRESS and the PCI host bridge connects that address to CONFIG_DATA for you to read and write. (The address selects the slot, among other things.)

jaihsonk wrote:Where can I read the PCI device structure from? Or is the structure composed of data from multiple ports?

You read it from CONFIG_DATA.