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Hello,
I would like to know what is the technical difference(s) between CISC and RISC?
Thanks for any help.

CISC has a lot of instructions that frequently overlap, CISC artchitectures are easier to program in assembly because of the "complex" instructions which consume many of the smaller steps that would have been required otherwise.

RISC is a minimalist, it only provides the basic set you need without the "complex" instructions, these architectures are generally faster than CISC because there are only 20 or so instructions that the CPU designer needs to optimise. CISC can have hundreds but the complex instructions are often slower than just using the primitive instructions (mov, push, add, sub, mul, etc) to do it yourself.

http://cse.stanford.edu/class/sophomore ... /risccisc/

Note that the two big players in the desktop world (x86 and PPC) are, both of them, neither RISC nor CISC. x86 is a CISC frontend powered by a RISC backend (i.e., the CISC instruction set is basically emulated by a RISC engine), and the PPC started out as RISC but in the meantime has grown to sport almost as many instructions as the x86... ::)

RISC contains only a few instructions of the types:

load
store
maths (add/sub etc.)
logic
conditional branching

Using these, you can compose the others. Multiply is a series of adds, shifts and ands, divide is similarly defined etc.

It's funny how CISC processors often run fastest when programmed like a RISC (that is, only use RISC-like instructions).

But really, modern CISC front -> RISC backend x86 is a beauty in some ways, because RISC architectures also insists on things like fixed instruction size, and this can lead to some bloat in code size, which in turn means you need more code-cache and your instruction fetch times can increase a bit and everything.

Now, on a modern x86, you basicly load the code in quite economic CISC form, so you get smaller code, but then you decode it internally into RISC, and you can still apply all (or most) optimizations that RISC allows you. Sure, you need an overly complicated instruction decoder, and some extra pipelines and caches, and dependency analysis and what not, but the result is basicly best of both worlds.

The only problem is that the compiler backend is now slightly hard to update... since the CISC->RISC module within the processor is essentially a Just-In-Time compiler.

Which now gives us some insights into what RISC is all about: it's all about pushing as much as possible away from the processor, into the software. Some RISC architectures even let you load TLB entries from software... in fact page faults degenerate into TLB faults, which the operating then needs to handle.

Basicly, RISC is about making it simple for the chip designers, while CISC is about making it simple for the programmers.

Oh, and if you really don't have a MUL in your RISC architecture, then the architecture sucks even as a RISC. There is a point after which reducing an instruction set futher is so costly that there is simply no point.

MUL (or DIV) is a good example, as they are insanely faster when implemented directly in hardware, and even then they tend to be slow enough that you'd prefer avoiding them where possible, especially with lower-end CPUs.

In short, you can safely have MUL and DIV and still claim it RISC.