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I'm writing an assembly routine to set up the 8259 PIC chip using the following information: https://www.eeeguide.com/programming-8259/
I'm a bit confused as to what it could mean by the "interrupt vector address" -- wiki.osdev mentions this same thing in the 8259 programming tutorial.
The reason this confuses me is, why would the PIC need to know any kind of memory address? I was under the impression that the PIC simply sent an offset to the CPU, and the CPU added that offset to the base address of the IDT to get the ISR (oh yes I should've mentioned I'm in 32-bit protected mode, so am setting up an IDT rather than an IVT, if that matters.)
So my question is, what is the interrupt vector address? And out of interest, what is it by default?

It's not a memory address in ICW2. It's the base interrupt number (bits 7 through 3 of it; bits 2 though 0 are zeroes). By default the interrupt numbers are 0x08+0...7 (for master PIC/IRQ0...7) and 0x70+0...7 (for slave PIC/IRQ8...15).

alexfru wrote:It's not a memory address in ICW2. It's the base interrupt number (bits 7 through 3 of it; bits 2 though 0 are zeroes). By default the interrupt numbers are 0x08+0...7 (for master PIC/IRQ0...7) and 0x70+0...7 (for slave PIC/IRQ8...15).

Ooooh, thank you so much!
Would it be useful to change the addresses from the default? I think I read somewhere that the 0x08+0...7 addresses are reserved by the CPU or something, would it perhaps be a good idea to change the interrupt numbers for the master PIC to 0x80+0...7?
And just to make sure I'm absolutely certain here - say my PICs are configured to their default address settings, and IRQ0 interrupts, the CPU would then look up the 0x08th entry in the IDT?
Thanks!

EDIT: I just worked out the answer to my first question there, yes the first 32 interrupts are reserved to be interrupts for exceptions