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Hi,

i am in long mode and i would work with data located in RAM, i understood i had to use paging. I have some questions about paging: in protected mode we use CR3 register to locate data, in long mode what is the equivalent ? Once we did that where does data go to allow us to use them ? And last questions, what is what we call "entry" for exemple in page dictory entry and page table entry, where are they located in RAM again in long mode and can we work without them ?

You still use CR3 to store the address of your page table. It is essential that you consult the Intel or AMD manuals to understand the structure of the page tables in long mode. It is essentially the same as protected mode, but another level of table is required to manage the larger address space.

ComputerMail wrote: And last questions, what is what we call "entry" for exemple in page dictory entry and page table entry,

Each "level" of page tables has entries pointing to the next level of page tables or, at the lowest level, the page itself.

ComputerMail wrote: where are they located in RAM again in long mode?

Wherever you put them. cr3 points to the highest level, and the entries in that level point to the next one, and so on and so forth.

ComputerMail wrote: and can we work without them ?

No, they're required in long mode.


Here's a brief example of what entries are and where they are: Let's say you want the virtual address 0 to be mapped to 12345678000h and you want your page tables to be in the first 16KB of RAM: Viewed from another angle, here's how a virtual address is translated:

I prefer the benefits of paging, but if you don't want to deal with it then you can effectively work without it. Simply use huge pages and statically identity map (where virtual address = physical address) all of the possible address space, then point CR3 to that and you're done. After that you only have to make sure not to overwrite the tables.

Thank you a lot for answers, i read Intel® 64 and IA-32 Architectures Software Developer’s Manual but i don't really understand what are written in. For more informations my operating system is just a program who is able to boot, i need to use RAM by specifical way, exact way is: i put 64bits value in a register that look at conresponding address, read first bits where are just written if it is data or code and size of block data or code of that address then put that block somewhere to allow me to use them. Is it possible to do a thing like that ?

I see pages entry take RAM memory, is it really no working if i do not use them ? So i think i understand paging, example of 32 bits, first i put 32 bits address in CR3, then i go along any octets by changing pointer register, is it correct ?

So i just see i only need to address 64go thus staying in protected mode will suffice, is there other way to address RAM as pagination ?

ComputerMail wrote:is there other way to address RAM as pagination ?

No. To quote the wiki on this,

Wiki wrote:Using paging has become mandatory, and segmentation has been stripped down for performance reasons.

Paging is your only way to go.

ComputerMail wrote:to address 64go thus staying in protected mode will suffice

Proper spelling and grammar would have made this clearer for me. Assuming you mean 64 GiB, no. Protected Mode virtual addresses are 32-bit, i.e. you're limited to 4 GiB.

ComputerMail wrote:For more informations my operating system is just a program who is able to boot

Smells like a typical use case for UEFI.

Of course there's PAE which does allow access to 64GiB of physical memory, but only 4GiB at a time. Even a single process can access all of it but that might be too much of a hassle, at which point long mode is probably a better idea.

I only need to r/w in 64go RAM, by using PAE that would be possible you say. If i have to do operation on two dw being themselves in different 4go blocks, is it faster in 32bits or 64bits ? Also i do not really need to understand how do all that work, i would just use RAM in faster mode for given example in assembly language (nasm) if it is easier to answer.

There is just so much wrong with this. Let's go through it step by step:

ComputerMail wrote:I only need to r/w in 64go RAM

What unit is 'go'? Google doesn't really give me an answer. There are bits: they are single binary digits. A byte is essentially nothing but a 8-digit binary number. All the prefixes are just the regular metric prefixes, i.e. a power of ten. The slightly changed ones (e.g. Kibibyte) are far less common and based on powers of two. Long story short: 8 bit = 1 byte, 1000 bytes = 1 KB, 1024 bytes = 1 KiB.

ComputerMail wrote:Also i do not really need to understand how do all that work

This is the wrong mindset altogether. As someone (I honestly don't remember who) said, osdev is 90% research. Lazy design and bad code will bite you really badly at some point down the road.

ComputerMail wrote:i would just use RAM in faster mode for given example in assembly language (nasm) if it is easier to answer.

There probably is no general answer to this, as this depends on many aspects of the CPU and RAM. You should have a good idea of what you're targeting, as the very first line of your code is completely arch-dependent. You should pick whatever platform you want to run your OS on. There are multiple factors here, e.g. if you want to use more than 4 GiB of memory, you have to go with 64-bit. If you want to use Virtual 8086 Mode, you'll have to go with 32-bit.

Although I don't really get what you're trying to say about PAE, but I can tell you that there's a catch: you can only use (as in page) 4 GiB of memory at a time, as virtual addresses are still locked to 32-bit (hence the name 'Physical Address Extension').

While it's not my job to do this, I really have to ask you this: have you read Beginner_Mistakes and Required_Knowledge?

Edit: I found the quote:

eryjus wrote:I would characterize writing a Hobby OS more of a research project than a coding project.

ComputerMail wrote: If i have to do operation on two dw being themselves in different 4go blocks, is it faster in 32bits or 64bits ?

that is not how PAE works... if you have 2 DWs, no matter where they are located, you can access both at the same time

PAE doesn't use 4GB blocks, it uses 4KB blocks, and you can map up to a million blocks at a time (if you need more than a million 4KB blocks, then you will need to unmap some blocks to map others in -- a technique called 'memory banking')

however, in general, unless you need a specific deprecated feature, LMode is going to be faster than PMode, though not as much faster as PMode is faster than RMode/UMode (which is by far the slowest)

LMode is also going to be much easier to use than PMode (regardless of whether you are using PAE or not)
Paging is easier to use than not-paging (even though at first, paging seems very complicated, it is still far easier to learn paging than to not use paging)

accessing more than 4GB of address space (note address space is not the same as RAM) in PMode using PAE or PSE-36 is going to be more complicated, and will require you to use banking techniques to map in and out various parts of memory -- meaning it will be both much harder and much slower (since changing the mapping incurs performance penalties)