Spinlock + disable irq in user space w. timeout
Posted: Mon Jan 09, 2017 7:31 am
The spinlock as it is now is pretty much useless in user space because of you can get a context switch inside the lock and then have unpleasant side effects due to that like priority inversion. In kernel space the spinlock is however often used and this always in conjunction together with disabling the interrupts. In kernel space this is often an acceptable solution and does not block interrupts for too long if used correctly on simple data structures.
I've seen that some processor manufacturers have implemented transactional memory like Intel TSX. The HW complexity of implementing this is probably pretty high. There have also been some studies that many lockless algorithms perform worse than the non-lockless version and just taking the lock. Also many processor designers refuse to go beyond the CAS and not even implementing a DCAS.
One question is how to enable the spinlock for the user space world as it is a simple but quite versatile if we can get it to work. So what I would think of is adding a functionality in the processor that allows user space processes to disable the interrupts for X amount of instructions ahead. The amount of allowed instructions allowed can be defined by the operating system by configuring the CPU. Each CPU could just have machine status register that counts the number of instructions inside the lock which is part of the context and of course cannot be altered by user processes. If X amount of instructions are reached inside the lock, a processor exception happens and the OS needs to decide what to do.
Have you seen such functionality in any more unusual ISAs? Do you see any pitfalls in with this functionality?
I've seen that some processor manufacturers have implemented transactional memory like Intel TSX. The HW complexity of implementing this is probably pretty high. There have also been some studies that many lockless algorithms perform worse than the non-lockless version and just taking the lock. Also many processor designers refuse to go beyond the CAS and not even implementing a DCAS.
One question is how to enable the spinlock for the user space world as it is a simple but quite versatile if we can get it to work. So what I would think of is adding a functionality in the processor that allows user space processes to disable the interrupts for X amount of instructions ahead. The amount of allowed instructions allowed can be defined by the operating system by configuring the CPU. Each CPU could just have machine status register that counts the number of instructions inside the lock which is part of the context and of course cannot be altered by user processes. If X amount of instructions are reached inside the lock, a processor exception happens and the OS needs to decide what to do.
Have you seen such functionality in any more unusual ISAs? Do you see any pitfalls in with this functionality?