You have a 50-year-old IBM mainframe in your cell phone
Posted: Mon Dec 08, 2014 11:43 am
Will Edwards from Mill Computing will be giving a talk on a revolutionary computer architecture.
When: 14:00-15:00 with discussion afterwards, 10th December 2014
Where: ICT building room ICT-507AB, Tallinn Tech, Akadeemia tee 15a, Tallinn, Estonia.
Every architectural part of current CPUs was present in the System/360 – caches, out-of-order execution, large register files, byte addressing, even hexadecimal. All the advances of the last 50 years have been in the fabrication process – how CPUs get made, not how they work. Isn’t it about time to bring the architecture up to date too?
This talk introduces the new Mill CPU architecture which brings DSP-like efficiency and performance to general purpose computing. Offering a 10x power/performance gain over conventional out-of-order superscalar architectures, the Mill family of CPUs scales from phones to supercomputers.
The Mill is an extremely wide-issue VLIW design, able to issue 30+ MIMD operations per cycle. The Mill is inherently a vector machine and can vectorize and pipeline almost all loops in general purpose code. The Mill is a belt machine (as distinct from a stack or register machine) and has a fine grained security model that facilitates microkernels without performance penalties.
This talk will give a high-level introduction to the Mill programming model, with an opportunity for the audience to ask more detailed questions in areas of interest.
Will is a technical member of the Mill CPU team.
Videos and other material about other aspects of the Mill can be found at http://millcomputing.com/docs.
When: 14:00-15:00 with discussion afterwards, 10th December 2014
Where: ICT building room ICT-507AB, Tallinn Tech, Akadeemia tee 15a, Tallinn, Estonia.
Every architectural part of current CPUs was present in the System/360 – caches, out-of-order execution, large register files, byte addressing, even hexadecimal. All the advances of the last 50 years have been in the fabrication process – how CPUs get made, not how they work. Isn’t it about time to bring the architecture up to date too?
This talk introduces the new Mill CPU architecture which brings DSP-like efficiency and performance to general purpose computing. Offering a 10x power/performance gain over conventional out-of-order superscalar architectures, the Mill family of CPUs scales from phones to supercomputers.
The Mill is an extremely wide-issue VLIW design, able to issue 30+ MIMD operations per cycle. The Mill is inherently a vector machine and can vectorize and pipeline almost all loops in general purpose code. The Mill is a belt machine (as distinct from a stack or register machine) and has a fine grained security model that facilitates microkernels without performance penalties.
This talk will give a high-level introduction to the Mill programming model, with an opportunity for the audience to ask more detailed questions in areas of interest.
Will is a technical member of the Mill CPU team.
Videos and other material about other aspects of the Mill can be found at http://millcomputing.com/docs.
