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It said on wikipedia that a word can be 8,16,24,32,64 bits on modern processors. a DMA controller also does its transfers one word at a time. My question is , how does the DMA controller know to read/write a certain amount of words that the processor gives it when a word can be any of the above values that I mentioned? I heard about data alignment and structure padding. Would there be some padding added to the data so that it could read/write a bunch of 32 bit words evenly ? and i,m not really sure if data alignment plays a part in this or not.

I suggest you read a little more into 'the' DMA controller (DMA is just a term for a device getting direct access to the main memory, the original PC had a special DMA chip, but modern hardware tends to use PCI bus-mastering for DMA).

Anyway, read into the definition of a word for the hardware you're using.

alright. I'll do that. thx.

Hi,

Please realize that everyone disagrees what exactly a 'word' is. You appear to be using the definition that it is the size of the native machine register (32-bit on 32-bit systems, 64-bit on 64-bit systems). However in the Intel/Microsoft/Windows world, a world is a 16-bit value. Hence you get to see weird terms such as dword (32-bit) and qword (64-bit) even on Intel systems that is 32-bit and 64-bit. This is just plain silly and I urge people never to use the term 'word', but just call it a 16-bit value if that's what they mean.

Now you know how to understand the information you have misunderstood. When you read it transfer a word at a time, you mean that an ancient and obsolete interface does that (which some newer implementations may inefficiently emulate), where a word is a 16-bit value. There is no connection between word size on the DMA controller and whatever the native word size on the CPU is, it's all a matter of badly made definitions.