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what does memory mapped i/o mean? when the address is mapped does that mean that the i/o device sends data to a location in RAM dedicated for MMIO and then the cpu reads from that location? Or does it mean that the i/o control register is assigned a physical address so the cpu reads directly from the device?

The latter.

so the cpu basically reads from the i/o control register and sees that its assigned to a specific physical address...then it writes the data to that address?

from what ive been reading...in the case of memory mapped i/o... a certain portion of the processor's address space is mapped to the device, and communications occur by reading and writing directly to/from those memory areas. So basically the device can read/write to memory and the cpu reads/writes those memory locations. So for example, the cpu would write to a memory location and the the device would read from it. That is what it sounds like to me.

You might wonder how the communication might work. Suppose you have a printer, and it has some status bits. These bits may reside at some memory address that the CPU "knows" is for the printer. Thus, to get information from the printer, you read a byte or a word from that address.

That byte might tell you if the printer is printing, or is out of paper, or out of toner, or what kind of paper is being used, etc.

You may also want to direct the printer to print. You can send it what characters to print, or what font, etc. This information can be written to a "memory" address. However, instead of having memory at that address, you have an I/O device. The CPU acts as if its writing to memory, and the I/O device reads this information.

Regarding this I always thought that when we allocate some ranges of physical memory address to I/O, how can we we access the memory which resides in those portions of memory?

icealys wrote:so the cpu basically reads from the i/o control register and sees that its assigned to a specific physical address...then it writes the data to that address?

The OS has first to determine which memory address the registers of the chip are mapped to. In a modern PC it does this by reading the PCI configuration space. Then it just addresses the registers as if they were RAM.

It's not quite that straightforward, as some registers may be read only; with others writing a particular value to a register clears it, resets the chip, or some other action. So writing 12345 (random example) to the "memory" location doesn't necessarily mean that a read of that location will return 12345. The documentation for the device will detail this.

siavoshkc wrote:Regarding this I always thought that when we allocate some ranges of physical memory address to I/O, how can we we access the memory which resides in those portions of memory?

You need to understand the difference between physical memory (RAM) and physical address space (bus).

RAM is mapped into the physical address space by the firmware, which initializes the DRAM controller. Before this happens the firmware is usually limited to using the CPU's caches as RAM.

icealys wrote:from what ive been reading...in the case of memory mapped i/o... a certain portion of the processor's address space is mapped to the device, and communications occur by reading and writing directly to/from those memory areas. So basically the device can read/write to memory and the cpu reads/writes those memory locations. So for example, the cpu would write to a memory location and the the device would read from it. That is what it sounds like to me.

If the CPU tries to write to (or read from) a location used by a memory mapped device, the write will be intercepted before it reaches memory. It will be sent to the device instead. The circuitry which does that would once upon a time been in an external chip, but it is nowadays quite likely to reside in the CPU itself.

Brynet-Inc wrote:

siavoshkc wrote:Regarding this I always thought that when we allocate some ranges of physical memory address to I/O, how can we we access the memory which resides in those portions of memory?

You need to understand the difference between physical memory (RAM) and physical address space (bus).

RAM is mapped into the physical address space by the firmware, which initializes the DRAM controller. Before this happens the firmware is usually limited to using the CPU's caches as RAM.

Can you point me to a book or a guide about this topic? I am reading Intel manuals maybe I will reach to that too?

If the CPU tries to write to (or read from) a location used by a memory mapped device, the write will be intercepted before it reaches memory. It will be sent to the device instead.

so what happens to the physical locations in RAM? lets say you are reading from the device...so instead of accessing RAM it will read from the device and write to the physical location its mapped to?

siavoshkc wrote:Can you point me to a book or a guide about this topic? I am reading Intel manuals maybe I will reach to that too?

You might find it in the Bios Writer's Handbook (if there is such a thing). Because it executes in ROM, it alone can run prior to the RAM chips being initialised, and it alone can initialise them.

icealys wrote:so what happens to the physical locations in RAM? lets say you are reading from the device...so instead of accessing RAM it will read from the device and write to the physical location its mapped to?

Nothing happens to the physical locations in RAM. They just don't get used - unless it gets mapped elsewhere. From the firmware's point of view at system startup, memory chips constitute just one more type of device, waiting to be mapped into the processor's address space.

mathematician wrote:

siavoshkc wrote:Can you point me to a book or a guide about this topic? I am reading Intel manuals maybe I will reach to that too?

You might find it in the Bios Writer's Handbook (if there is such a thing). Because it executes in ROM, it alone can run prior to the RAM chips being initialised, and it alone can initialise them.

More about the definition of Physical Address Space I intend.

icealys wrote:

If the CPU tries to write to (or read from) a location used by a memory mapped device, the write will be intercepted before it reaches memory. It will be sent to the device instead.

so what happens to the physical locations in RAM? lets say you are reading from the device...so instead of accessing RAM it will read from the device and write to the physical location its mapped to?

I think you were given a very strange explanation. I don't know what this interception is. If you want to understand memory mapped I/O it is probably best to grab a microprocessor and build a computer which has an external chip on the main bus, e.g., memory, serial port, ADC, etc. What usually happens when the CPU reads or writes from a bus device is:

i) the CPU dumps a physical address onto the bus, then
ii) address decode logic maps the address to a chip select which tells a bus device that the CPU is talking to it, then
iii) the selected device does what it needs to do.

From this you see that memory is no different from any other device on the bus. Things aren't intercepted before they reach memory, everything on the bus is reached at the same time, the decode logic selects the device that is being communicated with. Here, I've assumed a processor bus as you asked about memory mapped devices, but other buses like I2C or ethernet are similar, there's always some kind of decode logic somewhere: either centralised with chip selects on a processor bus or localised like I2C or ethernet.

For an example, look at the following spec. sheet for an ADC chip: http://www.ti.com/cn/lit/gpn/adc0804-n. See page 27 (microprocessor interfacing) for memory mapped operation and I/O port operation. Page 2 (typical applications) gives the high-level interfacing details.

i'm a little confused on something, so for example, an input device sends a signal to the processor and the processor reads from the input device like a mouse or keyboard? OR, does the device send data to the processor?