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Hi all,

I have a question regarding PAE. In the Wiki (http://wiki.osdev.org/Setting_Up_Paging_With_PAE) the PDPT has only one entry with the "present" bit set to 1. The other 3 entries are unused and thus it seems that they are not required to be present. However, when looking up the PDPT in the Intel manual (https://communities.intel.com/servlet/J ... amming.pdf page 3-35) it says:

The present (P) flag (bit 0) in all page-directory-pointer-table entries must be set to 1 anytime extended physical addressing mode is enabled; that is, whenever the PAE flag (bit 5 in register CR4) and the PG flag (bit 31 in register CR0) are set. If the P flag is not set in all 4 page-direc- tory-pointer-table entries in the page-directory-pointer table when extended physical addressing is enabled, a general-protection exception (#GP) is generated.

So that seems to indicate one would need to make 4 valid page directories before enabling PAE. If they are unused, it seems that they should point to an all-zero page directories (at least none of the pages being marked present), and the entries in the PDPT pointing to these all-zero page directories with the present bit being set to 1.
Is this correct? If so, it seems the Wiki is slightly wrong. But then again, I've tried the Wiki's method and it works fine. So is this simply undefined behaviour (even though it specifically says an exception must be generated)? Or am I missing something here?

Thanks in advance

The version I have of the intel manuals (June 2010, Vol 3A, section 4.4) does not mention this requirement. So according to that, the tutorial is correct.

Hi,

thepowersgang wrote:The version I have of the intel manuals (June 2010, Vol 3A, section 4.4) does not mention this requirement. So according to that, the tutorial is correct.

This is the first time I've noticed a "present bits in PDPT entries must be set" requirement; so I did some more checking.

It seems Intel manuals from 2002 and earlier do say the present bit must be set, and manuals from 2004 and later say it can be set or clear. For the 2004 manual, "Chapter 18, IA-32 Compatibility" has no mention of any older CPUs requiring the present bit set (but does have various compatibility differences going back to 8086). For all manuals, the section in the "exception reference" that lists all of the possible causes of a general protection fault doesn't mention anything about general protection faults caused by PDPT entries that were clear (even though they do include things like "Setting any reserved bits in PDPT entries to 1 when PAE is enabled causes GPF").

For these reasons I'm tempted to assume that the older manuals were wrong, the mistake was corrected between 2002 and 2004, and there never was a requirement for the present bits in PDPT entries to be set.


Cheers,

Brendan

Ok, good to know. Thanks for the answers, guys!