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Bochs question

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Bochs question

Posted: Thu Oct 03, 2013 8:26 pm
by teodori
Hello when I am switching from compatibility mode to 64 bit submode in bochs, it gives me following answer:

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00259400000i[CPU0 ] CPU is in long mode (halted)
00259400000i[CPU0 ] CS.d_b = 16 bit
00259400000i[CPU0 ] SS.d_b = 16 bit
00259400000i[CPU0 ] EFER   = 0x00000501
00259400000i[CPU0 ] | RAX=00000000e0000010  RBX=0000000000200003
00259400000i[CPU0 ] | RCX=00000000c0000080  RDX=0000000000000000
00259400000i[CPU0 ] | RSP=0000000000000200  RBP=0000000000000099
00259400000i[CPU0 ] | RSI=00000000000e00bb  RDI=0000000000006000
00259400000i[CPU0 ] |  R8=0000000000000000   R9=0000000000000000
00259400000i[CPU0 ] | R10=0000000000000000  R11=0000000000000000
00259400000i[CPU0 ] | R12=0000000000000000  R13=0000000000000000
00259400000i[CPU0 ] | R14=0000000000000000  R15=0000000000000000
00259400000i[CPU0 ] | IOPL=0 id vip vif ac vm rf nt of df if tf SF zf af PF cf
00259400000i[CPU0 ] | SEG selector     base    limit G D
00259400000i[CPU0 ] | SEG sltr(index|ti|rpl)     base    limit G D
00259400000i[CPU0 ] |  CS:0008( 0001| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  DS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  SS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  ES:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  FS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  GS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00259400000i[CPU0 ] |  MSR_FS_BASE:0000000000000000
00259400000i[CPU0 ] |  MSR_GS_BASE:0000000000000000
00259400000i[CPU0 ] | RIP=0000000000007ebc (0000000000007ebc)
00259400000i[CPU0 ] | CR0=0xe0000011 CR2=0x0000000000000000
00259400000i[CPU0 ] | CR3=0x00002000 CR4=0x000000a0
00259400000i[CPU0 ] 0x0000000000007ebc>> jmp .-3 (0x0000000000007ebb) : EBFD
00259400000i[CMOS ] Last time is 1380853374 (Fri Oct  4 04:22:54 2013)
00259400000i[     ] restoring default signal behavior
00259400000i[CTRL ] quit_sim called with exit code 1
does this mean I am in 64 bit submode or not, because CS.d_b is 16 bit???

Re: Bochs question

Posted: Thu Oct 03, 2013 11:13 pm
by xenos
Which Bochs version are you using? My output from 2.6.2 looks like this:

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i02027436000:[CPU0 ] CPU is in long mode (halted)
i02027436000:[CPU0 ] CS.mode = 64 bit
i02027436000:[CPU0 ] SS.mode = 64 bit
i02027436000:[CPU0 ] EFER   = 0x00000501
And what does your code look like, that takes you to 64 bit mode - and the code descriptor of your 64 bit code segment?

Re: Bochs question

Posted: Fri Oct 04, 2013 2:35 pm
by teodori
Bochs x86 Emulator 2.4.6

64 bit GDT

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	# Null Descriptor
	.word 0x0000, 0x0000
	.byte 0x00, 0b00000000, 0b00000000, 0x00
	# Code Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10011010, 0b10101111, 0x00
	# Data Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10010010, 0b10101111, 0x00
Oh the output is different, you got:

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CS.mode = 64 bit
SS.mode = 64 bit
but I got:

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CS.d_b = 16 bit
SS.d_b = 16 bit

Re: Bochs question

Posted: Fri Oct 04, 2013 11:19 pm
by xenos
teodori wrote:Bochs x86 Emulator 2.4.6
Looks like your Bochs version is rather old... You should consider using an up-to-date one.
64 bit GDT

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	# Null Descriptor
	.word 0x0000, 0x0000
	.byte 0x00, 0b00000000, 0b00000000, 0x00
	# Code Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10011010, 0b10101111, 0x00
	# Data Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10010010, 0b10101111, 0x00
Also here we differ. Using your notation, this is my GDT (basically - see entries 0x20 and 0x30 in my code)

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	# Null Descriptor
	.word 0x0000, 0x0000
	.byte 0x00, 0b00000000, 0b00000000, 0x00
	# Code Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10011010, 0b00101111, 0x00
	# Data Descriptor
	.word 0xffff, 0x0000
	.byte 0x00, 0b10010010, 0b11001111, 0x00
...but the difference should concern only fields that are ignored anyway.

Re: Bochs question

Posted: Sun Oct 06, 2013 12:54 pm
by teodori
Ok using bochs 2.6.2 doesn't work, I got a read/write to Model Specific Register error:

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00014090085i[BIOS ] Booting from 0000:7c00
00014173232e[CPU0 ] RDMSR MSR_EFER: EFER MSR is not supported !
00014173232e[CPU0 ] RDMSR: Unknown register 0xc0000080
00014173235e[CPU0 ] SetEFER(0x00000101): attempt to set reserved bits of EFER MSR !
00014173235e[CPU0 ] interrupt(): gate descriptor is not valid sys seg (vector=0x0d)
00014173235e[CPU0 ] interrupt(): gate descriptor is not valid sys seg (vector=0x08)
00014173235i[CPU0 ] CPU is in protected mode (active)
00014173235i[CPU0 ] CS.mode = 32 bit
00014173235i[CPU0 ] SS.mode = 32 bit
00014173235i[CPU0 ] EFER   = 0x00000000
00014173235i[CPU0 ] | EAX=00000101  EBX=00200003  ECX=c0000080  EDX=00000000
00014173235i[CPU0 ] | ESP=00000200  EBP=00000099  ESI=000e00bb  EDI=00006000
00014173235i[CPU0 ] | IOPL=0 id vip vif ac vm RF nt of df if tf sf zf af pf cf
00014173235i[CPU0 ] | SEG sltr(index|ti|rpl)     base    limit G D
00014173235i[CPU0 ] |  CS:0008( 0001| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] |  DS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] |  SS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] |  ES:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] |  FS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] |  GS:0010( 0002| 0|  0) 00000000 ffffffff 1 1
00014173235i[CPU0 ] | EIP=00007e7f (00007e7f)
00014173235i[CPU0 ] | CR0=0x60000011 CR2=0x00000000
00014173235i[CPU0 ] | CR3=0x00002000 CR4=0x00000000
00014173235i[CPU0 ] 0x00007e7f>> wrmsr  : 0F30
00014173235p[CPU0 ] >>PANIC<< exception(): 3rd (13) exception with no resolution

Re: Bochs question

Posted: Sun Oct 06, 2013 1:00 pm
by Nable
Upd:
It seems that you've chosen wrong CPU in your .bochsrc:
cpu/msr.cc +252:

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    case BX_MSR_EFER:
      if (! BX_CPU_THIS_PTR efer_suppmask) {
        BX_ERROR(("RDMSR MSR_EFER: EFER MSR is not supported !"));
        return handle_unknown_rdmsr(index, msr);
      }
      val64 = BX_CPU_THIS_PTR efer.get32();
      break;
cpu/init.cc +755:

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  BX_CPU_THIS_PTR efer.set32(0);
  BX_CPU_THIS_PTR efer_suppmask = 0;
  if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_NX))
    BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_NXE_MASK;
  if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_SYSCALL_SYSRET_LEGACY))
    BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_SCE_MASK;
#if BX_SUPPORT_X86_64
  if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_LONG_MODE)) {
    BX_CPU_THIS_PTR efer_suppmask |= (BX_EFER_SCE_MASK | BX_EFER_LME_MASK | BX_EFER_LMA_MASK);
    if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_FFXSR))
      BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_FFXSR_MASK;
    if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_SVM))
      BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_SVME_MASK;
  }
#endif

Re: Bochs question

Posted: Sun Oct 06, 2013 1:09 pm
by teodori
Nop :-) missing config option before compile:

Code: Select all

#!/bin/bash
rm -rf bochs-2.6.2
tar -xJf bochs-2.6.2.tar.xz
cd bochs-2.6.2
./configure --enable-x86-64 --with-all-libs --prefix /opt
make -j4
cd ..
now I get:

Code: Select all

00014090084i[BIOS ] Booting from 0000:7c00
00014173259i[CPU0 ] WARNING: HLT instruction with IF=0!
00834004000p[SDL  ] >>PANIC<< User requested shutdown.
00834004000i[CPU0 ] CPU is in long mode (halted)
00834004000i[CPU0 ] CS.mode = 64 bit
00834004000i[CPU0 ] SS.mode = 64 bit
00834004000i[CPU0 ] EFER   = 0x00000501
00834004000i[CPU0 ] | RAX=00000000e0000010  RBX=0000000000200003
00834004000i[CPU0 ] | RCX=00000000c0000080  RDX=0000000000000000
00834004000i[CPU0 ] | RSP=0000000000000200  RBP=0000000000000099
00834004000i[CPU0 ] | RSI=00000000000e00bb  RDI=0000000000006000
00834004000i[CPU0 ] |  R8=0000000000000000   R9=0000000000000000
00834004000i[CPU0 ] | R10=0000000000000000  R11=0000000000000000
00834004000i[CPU0 ] | R12=0000000000000000  R13=0000000000000000
00834004000i[CPU0 ] | R14=0000000000000000  R15=0000000000000000
00834004000i[CPU0 ] | IOPL=0 id vip vif ac vm rf nt of df if tf SF zf af PF cf
00834004000i[CPU0 ] | SEG sltr(index|ti|rpl)     base    limit G D
00834004000i[CPU0 ] |  CS:0008( 0001| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  DS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  SS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  ES:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  FS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  GS:0010( 0002| 0|  0) 00000000 ffffffff 1 0
00834004000i[CPU0 ] |  MSR_FS_BASE:0000000000000000
00834004000i[CPU0 ] |  MSR_GS_BASE:0000000000000000
00834004000i[CPU0 ] | RIP=0000000000007ebc (0000000000007ebc)
00834004000i[CPU0 ] | CR0=0xe0000011 CR2=0x0000000000000000
00834004000i[CPU0 ] | CR3=0x00002000 CR4=0x000000a0
00834004000i[CPU0 ] 0x0000000000007ebc>> jmp .-3 (0x0000000000007ebb) : EBFD
00834004000i[CMOS ] Last time is 1381086594 (Sun Oct  6 21:09:54 2013)
00834004000i[     ] restoring default signal behavior

Re: Bochs question

Posted: Sun Oct 06, 2013 3:15 pm
by xenos
teodori wrote:

Code: Select all

00834004000i[CPU0 ] CS.mode = 64 bit
00834004000i[CPU0 ] SS.mode = 64 bit
Looks good ;)

Re: Bochs question

Posted: Mon Oct 07, 2013 7:22 am
by teodori
Thanks for your support ;)
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