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I've been thinking about the design of the page mapping code for my ARM kernel, and I'm trying to decide if I should make use of all four of the available pages sizes or just use the largest and smallest sizes. As I understand it, the only real advantage of the middle page sizes is that they allow the processor to use TLB slots more efficiently than if the pages were mapped using the smallest size. Is this likely to have much of an effect on performance?

Yes, it affects performance for the reason you mentioned yourself. The easy solution is to allow locked memory to be optimized while unlocked memory to be 4KB only. Allowing mixed sized pages isn't impossible but it surely makes certain things more complex, like how to determine the swap out candidate for example.