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What I don't get is how the CPU has any part to play in generating message signalled interrupts. When a device writes to memory it will normally have to go through something like the north bridge controller, and it is that controller which would have to intercept a message signalled interrupt and raise a signal on one of the processor's interrupt pins. So it is the north bridge controller which would need to know about any addresses reserved for MSIs. And yet in the Intel manual it talks about the processor supporting message signalled interrupts, and specifying the addresses to which the messages should go.

What have I missed?

You have missed that most parts of north bridge (especially memory controller) is integrated into CPU nowadays.

Nable wrote:You have missed that most parts of north bridge (especially memory controller) is integrated into CPU nowadays.

Ta. It's always nice to know why something works.