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After reading some PowerPC manuals, here are what I understand about PowerPC segmentation model:

Program access memory by a 32-bit address called effective address. An effective address has two parts, a 4-bit segment selector and a 28-bit offset. So each segment is fixed size, 256 MB. This effective address is converted to a 52-bit virtual address. The convert process as follow:

From 4-bit segment selector, the processor will choose 1 segment register (SR) from total 16 SRs. So this segment selector is same as segment prefix in an instruction of Intel ISA. SR contain a 24-bit base of the segment in virtual address space, which is called Virtual Segment ID (VSID). VSID is concatenated with the 28-bit offset in effective address to form 52-bit virtual address.

So in basic, PowerPC has a 52-bit address space but you can only access it by 256 MB windows (segments). Therefore, this segmentation model isn't similar to 80386 model but 8086 model, which has a 20-bit address space but can only access by 64 KB segments. Am I correct?

By the way, are there another ISA which use segmentation model?

Congdm wrote:So in basic, PowerPC has a 52-bit address space but you can only access it by 256 MB windows (segments). Therefore, this segmentation model isn't similar to 80386 model but 8086 model, which has a 20-bit address space but can only access by 64 KB segments. Am I correct?

Not quite.

Such a system has been used on a multitude of CPUs. Basically by reserving bits of the 32-bit address space you actually chose a current configuration for the system bus as well. Memory could run at the full bus speed, devices could not, and the processor used the higher-order bits to index into a lookup table to see how much clock cycles it should wait between driving the bus.
To the code in question this simply shows a linear address space - devices were at an address several MBs higher and they could just see all of memory, and when they accessed it, the processor would perform the proper bus logic.

Now, if the divisions happen to occur in smaller intervals than the amount of RAM you have, then you'd simply configure each range with the same settings. When the processor would cross a boundary, the bus access would look up the controls, and happily proceeds with the same configuration. For all intents and purposes the memory appears contiguous despite segmentation taking place under the hood.

In it's original form it's basically the functional replacement of the MTRRs on x86. With the added address translation it's basically a form of paging with huge pages where you probably can - just like x86 - set caching controls on a per-page basis, and more.

So PowerPC segment is a some kind of huge page, right? After all, a page is a fixed size segment without bound checking. Are there any efficient way to bound checking in run-time without using segments?