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Hello, i would like to know in wich cases the cpu cache must be disabled or flushed.For example,page memory used by a pci device needs special settings like not cacheable or not.

Intel® 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, and 3C: System Programming Guide, Parts 1 and 2 - Chapter 11 - MEMORY CACHE CONTROL

Hi,

octavio wrote:Hello, i would like to know in wich cases the cpu cache must be disabled or flushed.For example,page memory used by a pci device needs special settings like not cacheable or not.

There are only 6 situations where caches need to be disabled that I know of:

• When you're changing memory controller configuration (which is only ever really done once by firmware during boot, when it detects RAM chips and configures the memory controller to suit).
• When you're changing MTRRs in an SMP system. This is a special series of steps that needs to be synchronised so that all CPUs do each step before any CPU starts the next step (something like "disable caches and do WBINVD on all CPUs, then load new MTRRs on all CPUs, then re-enable caches on all CPUs" - see the Intel manual for the exact sequence).
• For memory mapped IO. Typically you do the reverse here (e.g. the areas of the physical address space that may be used for memory mapped IO are "uncached" by default, and you change MTRRs to enable limited caching where beneficial, like making display memory "write-combining").
• When you're benchmarking RAM chip bandwidth (otherwise you can be benchmarking CPU cache bandwidth instead). This is a little tricky though - you'd want to disable caching for the RAM being benchmarked without disabling caching for the instructions doing the benchmarking. I'd assume most people just make sure the amount of RAM being benchmarked is larger than the size of the caches (so they know that anything cached will have been evicted before it's accessed again) rather than disabling any caches.
• When you're testing if RAM is faulty (otherwise you can be testing if CPU caches are faulty instead). For testing a large amount of RAM (larger than cache size) you don't actually need to disable caches.
• When it improves performance (helps to avoid cache pollution). Note: this is limited to selective cache disabling (e.g. using the page attributes for specific pages) or selective cache flushing (e.g. the CLFLUSH instruction).

For the last 3 cases, it's better to use "non-temporal moves" instead of disabling caches if/when possible.


Cheers,

Brendan

Thanks,but what happens with the DMA ,does de cpu needs to flush the cache after writting a buffer that will be transfered by the DMA?
what is the alternative for cpus not supporting the clflush instruction?

octavio wrote:Thanks,but what happens with the DMA ,does de cpu needs to flush the cache after writting a buffer that will be transfered by the DMA?
what is the alternative for cpus not supporting the clflush instruction?

Architecture dependent whether caches need flushing. All x86 CPUs are cache coherent with DMA; Other architectures (e.g. ARM) tend not to be.