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I've been reading The Elements of Computing Systems(http://www1.idc.ac.il/tecs). And as a part of the assignments,I implemented a CPU which runs Hack(Hack is the name of the CPU specification they give) code.It's pretty simple,with only 2 instructions.You can read about it's machine code & assembly language at http://www1.idc.ac.il/tecs/book/chapter%2004.pdf. I am going to write it's assembler now(in Perl).

I've attached the computer.To run it,download the software and chapter 4 & 5 and the hardware simulator guide from http://www1.idc.ac.il/tecs,extract the zip I have attached,open computer.hdl in the hardware simulator,load a assembly program and watch it run.To load an assembly program click on the file button in the RAM32K chip(just below the screen),set reset to 1,single step,set reset to 0, and watch your program run.

If you want to understand how it works,read Appendix A and open CPU.hdl.Memory.hdl and Computer.hdl just tie them together.The names of the pins I hope are descriptive,and sorry for the absence of comments.

It's the error of the people that wrote the description of the architecture, not your error, but:

The Hack computer is a von Neumann platform.

...

The Hack programmer is aware of two distinct address
spaces: an instruction memory and a data memory. Both memories are 16-bit wide
and have a 15-bit address space, meaning that the maximum addressable size of each
memory is 32K 16-bit words.

*headdesk

A computer architecture with separate instruction and data spaces is a Harvard architecture, not a von Neumann architecture.

I saw that too.

amd64pager wrote:I've been reading The Elements of Computing Systems(http://www1.idc.ac.il/tecs). And as a part of the assignments,I implemented a CPU which runs Hack(Hack is the name of the CPU specification they give) code.It's pretty simple,with only 2 instructions.You can read about it's machine code & assembly language at http://www1.idc.ac.il/tecs/book/chapter%2004.pdf. I am going to write it's assembler now(in Perl).

I've attached the computer.To run it,download the software and chapter 4 & 5 and the hardware simulator guide from http://www1.idc.ac.il/tecs,extract the zip I have attached,open computer.hdl in the hardware simulator,load a assembly program and watch it run.To load an assembly program click on the file button in the RAM32K chip(just below the screen),set reset to 1,single step,set reset to 0, and watch your program run.

If you want to understand how it works,read Appendix A and open CPU.hdl.Memory.hdl and Computer.hdl just tie them together.The names of the pins I hope are descriptive,and sorry for the absence of comments.

Computer.zip

Modeling CPU's\etc at gate level is silly. You can get about 10 times the amount of work done modeling the logic at the RTL (Register Transfer Level) in Verilog or VHDL. They provide C like semantics that (given proper coding practices\style) can be run through a synthesizer\route and place tool to produce gate level netlist, which can be used to make an ASIC or applied to an FPGA. Programming chips solely on the gate level is like programming in machine code.

Right now I'm about half way through this book. It's absolutely great at explaining what goes into designing a modern microprocessor architecture. It doesn't provide any code examples, although there is a limited amount of pseudo code, but it's not really necessary. Ive only been messing around in Verilog\Microarch for a week and a half and I completely understand it, and it has been very fun to read.