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hi all,

just a quick question. when dealing with ram in numa domains, how are they addressed in the cpu?

does a cpu have access to all ram in the normal access process, or do i only get to see a small portion of the total ram and talk to other cpus for access to other areas? or are both possible?

Merry Christmas

Hi,

cxzuk wrote:just a quick question. when dealing with ram in numa domains, how are they addressed in the cpu?

does a cpu have access to all ram in the normal access process, or do i only get to see a small portion of the total ram and talk to other cpus for access to other areas? or are both possible?

For all 80x86 machines (and cache coherent NUMA in general), all CPUs can access all RAM. In this case supporting NUMA is a performance optimisation (and an OS could do no optimisation for NUMA at all and treat it as plain SMP and still access everything, just with some extra performance penalties).


Cheers,

Brendan