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The addressing scheme of the 32/64-bit x86 architecture defines segmentation on top of paging: There exist different segments for code and data, but they all share one paged mapping of linear to physical addresses (defined by CR3), with each segment being defined by an offset and a limit within the linear address space.

How many architectures exist, however, that define segmentation in terms of paging? In other words:

1) The architecture is physically a von-Neumann architecture. Code or data can reside in any portion of physical memory. Processors with separate physical address spaces don't count.
2) The architecture is virtually a Harvard architecture like the x86, with separate segments for code and data, or has some other way in which the interpretation of addresses is context dependent (such as separate segments for user and kernel modes).
3) *Unlike* the x86, each segment is defined in terms of its own paged address space (rather than being mapped into a global paged address space, roughly equivalent to if the x86 had a copy of CR3 for each of CS, DS, ES, etc.).

I'm aware of basically only two architectures that are like this: The PDP-11 variants that had memory management (Which started out with separate page mappings for user and kernel address spaces, and in later models ended up with separate instruction and data spaces as well), and the Magic architecture (a homebrew TTL architecture with separate code and data page mappings).

Is anybody aware of any other such architectures?

How many architectures exist, however, that define segmentation in terms of paging?

SH4 for one divides 32-bit addresses into CTL:SEG:OFFSET (iirc 3:3:26), with paging optionally running on top of that meeting the first instantiation of your question. Furthermore, protection is to some extent performed at the translated address level.

However according to your third rule posted later, SH4 fails whereas x86 actually passes unlike what your comments suggest: you can configure segmentation such that there are separate address spaces for code and data, and if necessary, for any value of a segment register simply by having segments not overlap. And this use of segmentation is what made it a powerful tool in the right hands - there are actually operating systems out there with multiple address spaces sharing a single instance of CR3, simply by modifying segmentation and only giving each process a fraction of the total address space to work with. Your conflicting description therefore raises the question: what is your actual (scholarly) goal.



Confusions aside, 68k architecture is electronically capable of being equivalent to PDP-11 architecture. It depends on the implementation of the external MMU if you actually have different mappings for privileged and unprivileged execution. Basically you can get just that to work by abusing the supervisor pin on the chip as one of the address lines if the MMU is not otherwise aware. No doubt there are several external-MMU-designs that offer the same option - after all any safety-capable MMU has to be aware of the fact if current accesses are done with reduced privileges or not. Note that none of that is technically part of the processor architecture but rather the architecture of the system as a whole. I haven't done any serious research into PDP (no access to one) but it wouldn't surprise me if it actually had an external MMU working just as described.

linguofreak wrote:The addressing scheme of the 32/64-bit x86 architecture defines segmentation on top of paging: There exist different segments for code and data, but they all share one paged mapping of linear to physical addresses (defined by CR3), with each segment being defined by an offset and a limit within the linear address space.

How many architectures exist, however, that define segmentation in terms of paging?

When the 8086 was launched Intel wanted to hang onto a 16 bit architecture, so that it was backwards compatible with their previous 16 bit offerings, but, at the same time, they wanted a larger address space. They solved that problem by having segment registers which added another four bits onto the address bus, and at the same time gave the 8086 a relocation mechanism. When memory protection was introduced with the 80286 and 80386 the obvious thing to do was to make use of the already existing segment registers to implement that protection. However, because of its greater flexibility, paging was introduced with the 80486, and segmentation was retained for the sake of backwards compatability.

Today segmentation is usually ignored, and in the 64 bit processors it has been abandoned almost completely, so you can no longer make use of it even if you want to.

No, paging on the x86 was introduced with the 386.

Segmentation is still used to simulate NX/XD bit, OpenBSD uses it to implement W^X, so memory is either writable or executable by default, but not both.

Combuster wrote:

How many architectures exist, however, that define segmentation in terms of paging?

SH4 for one divides 32-bit addresses into CTL:SEG:OFFSET (iirc 3:3:26), with paging optionally running on top of that meeting the first instantiation of your question. Furthermore, protection is to some extent performed at the translated address level.

However according to your third rule posted later, SH4 fails whereas x86 actually passes unlike what your comments suggest: you can configure segmentation such that there are separate address spaces for code and data, and if necessary, for any value of a segment register simply by having segments not overlap. And this use of segmentation is what made it a powerful tool in the right hands - there are actually operating systems out there with multiple address spaces sharing a single instance of CR3, simply by modifying segmentation and only giving each process a fraction of the total address space to work with.

Yes, but I think I read somewhere (possibly a discussion on this forum) that the addition necessary to calculate the linear address when the segment offset is nonzero imposes a speed penalty on such operating systems as compared to ones that use pure paging. Is that true? The point of defining a paged address space for each segment would be to avoid said speed penalty.

Your conflicting description therefore raises the question: what is your actual (scholarly) goal.



Confusions aside, 68k architecture is electronically capable of being equivalent to PDP-11 architecture. It depends on the implementation of the external MMU if you actually have different mappings for privileged and unprivileged execution. Basically you can get just that to work by abusing the supervisor pin on the chip as one of the address lines if the MMU is not otherwise aware.

This counts. I suppose it didn't have any way of indicating to the MMU whether it was making an instruction fetch or a data access (allowing separate instruction and data spaces)?

No doubt there are several external-MMU-designs that offer the same option - after all any safety-capable MMU has to be aware of the fact if current accesses are done with reduced privileges or not. Note that none of that is technically part of the processor architecture but rather the architecture of the system as a whole. I haven't done any serious research into PDP (no access to one) but it wouldn't surprise me if it actually had an external MMU working just as described.

From the reading I've done, the PDP-11's memory management scheme was first introduced in an external MMU, then integrated into the processor in later models.