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After browsing the Wiki article on the global descriptor table, I found that the global descriptor table register contains the virtual address of the GDT. I was just curious as to why the hardware used this approach in protected mode rather than holding the physical address of the GDT in the GDTR. If it indeed holds a virtual address, then for each segment-based virtual-to-physical address translation, we would also have to translate the address of that found in the GDTR to a physical one. This seems to be inefficient and somewhat analogous to holding a virtual address of a current page directory in the cr3 register.

Thanks in advance for the insight.

The GDT is not accessed on every translation of a segment:offset address, but only when a segment register is loaded. The contents of the GDT entry (i.e., segment limits, DPL...) are then cached in a "shadow register" associated with each segment register.

The wiki turns out to be incorrect as far as virtual addresses and the most likely interpretation concern. LGDT takes a virtual address, the GDTR structure stores instead a linear address as segmentation can not apply recursively. In both cases, paging does apply so you can allocate and free memory for when you want to change entries in the tables, as well as keep the GDT (and LDT/TSSes) above 3G if your kernel is located there as well.

Anyway, fixed the wiki. Thanks for telling.