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Do cache exist when cpu is in real mode? Can i setup somehow memory cache without using PAT from paging?

If you would have read the manual, you'd know the answer would be yes and yes.

If you think logically about it, you'd know the answer would be yes and yes because an 486 has caches, runs mostly real mode and has no PAT.

where should look in manual? assuming its something diffrent than mtrr.
and i dont get the diffrence between WP and WT.

writes in wt bypass cache, while wp do both into cache and memory?

Hi,

a5498828 wrote:where should look in manual?

There's typically an entire chapter in Intel's manual called "MEMORY CACHE CONTROL". I think it's something about latrodectus hasselti (and explains why you might not want to trust females), but I could be wrong.

a5498828 wrote:and i dont get the diffrence between WP and WT.

WB or WP?

For WB (write-back), reads come from cache (and cause "cache line fills" if the data isn't already in the cache); and writes are written to cache only, and only actually written to RAM if/when it is evicted from the cache for some reason.

For WT (write-through), reads come from cache (and cause "cache line fills" if the data isn't already in the cache); and writes are written to both the cache and RAM. This causes a bit more bus traffic (e.g. if the same cache line is written to several times). If the data is evicted from cache for some reason then it can be discarded (it's not written to RAM a second time).

For WP (write-protected), reads come from cache (and cause "cache line fills" if the data isn't already in the cache); and writes are written to the physical address space (and not cache) where they presumably update any "shadow RAM" underneath the ROM (or maybe end up with a "master abort" from PCI or something). In this case, cache is not modified because the data is treated as read-only.

There's a hierarchy of cache controls; where anything at any level can reduce the amount of caching (but not increase it). The NW and CD flags in CR0 are the lowest level control - if they say nothing is cached or nothing can use write-back, then none of the other cache controls can change that. The next level is the fixed MTRRs and the variable MTRRs. The highest level is the PCT/PWT/PAT flags in paging structures.

If there is no paging (it's disabled, including when the CPU is in real mode), then the NW and CD flags in CR0, and the MTRRs, all still do exactly the same.


Cheers,

Brendan

ok whats the purpose of cache in write-protected?
if writes dont go to cache, how reads can read from it?

if i write something and it wont touch cache, reads will read old data...

or is it just ignoring writes? i can write, but it will never be read. as Read Only Memory states.

Hi,

a5498828 wrote:ok whats the purpose of cache in write-protected?
if writes dont go to cache, how reads can read from it?

For WP, reads fetch data from the physical address space (e.g from a ROM).

a5498828 wrote:if i write something and it wont touch cache, reads will read old data...

or is it just ignoring writes? i can write, but it will never be read. as Read Only Memory states.

If you write to ROM, do you honestly think the ROM will remember what you wrote?

The whole idea of WP is to cache something like ROM (to avoid fetching data from the ROM itself). If writing to ROM doesn't change the ROM, then writing to ROM shouldn't change corresponding data in the cache either.


Cheers,

Brendan