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Hi!

In my MP table I found 2 bus-entries, one for the PCI and other fo the ISA bus. When parsing the PCI tree, I find only one bus and on it a PCI-ISA bridge. Some of the functions of this PCI-ISA bridge are for IDE stuff and the other I just don't remember, and right now my bootstrap don't work so I can not tell what about are the another functions in the PCI-ISA Bridge/device.

So the question is, What I need to do with the PCI-ISA bridge, use the functions that provide to comunicate with devices on ISA bus or configure it like the PCI-PCI bridge to pass the messages to the ISA bus? I have not found the configuration header on the net, so even don't know if it have upstream/downstream bus register.

Cheers!

Hi,

smoothCoder wrote:In my MP table I found 2 bus-entries, one for the PCI and other fo the ISA bus. When parsing the PCI tree, I find only one bus and on it a PCI-ISA bridge. Some of the functions of this PCI-ISA bridge are for IDE stuff and the other I just don't remember, and right now my bootstrap don't work so I can not tell what about are the another functions in the PCI-ISA Bridge/device.

So the question is, What I need to do with the PCI-ISA bridge, use the functions that provide to comunicate with devices on ISA bus or configure it like the PCI-PCI bridge to pass the messages to the ISA bus? I have not found the configuration header on the net, so even don't know if it have upstream/downstream bus register.

Download a few datasheets for some Intel chipsets (e.g. newer and older) and compare them. For the PCI to LPC bridge, the first 48 bytes of PCI configuration space look "standard", while everything after that doesn't. Basically if you're messing with the PCI to LPC bridge you'll need different code for each chipset.


Cheers,

Brendan

This sounds bad.
Now I have to initialize and re-map the APICs for first time in my life. So I am a bit confused. At this point is not time to me for mess with non-standard chipset stuff.

So, can I just use the devices that appears as functions on the PCI-ISA Bridge without complicating my life? These functions have IRQs and memory/IO ports etc. It would be wonderfool if I can just skip this way a lot of job. I have to save time, you know. I want to have an hobby-OS done before the apocalipse of 2012


PD: I found the datashied about ICH10. It appears to be the thing I need to read(>800 pages). But now another question: Now can I know the model of southbridge that I have(from inside the OS, not reading the back of the laptop:)? My Host to PCI Bridge(in the virtual machine) is 82443BX, and I dont know if it use ICH2, ICH5 or 10,(in the datashied I have searched something about ICH*, but nothing) how can I know it?

What exactly are you trying to find behind a PCI to ISA bus?

As far as I know, there's not any important (or at all?) behind that bus that needs explicit configuration.
ISA devices typically seen on any recent box have very standard resource assignments (IO and IRQs) with
no PCI configuration necessary to use them (or at least the BIOS sets it up for you).

The MP Table information is just giving you the proper routing for device IRQs on both buses. ISA had (and has)
specific IRQs for connection to the PIC, but there's no such standard for IOAPIC. Usually the first 16 IOAPIC pins
will have all the ISA IRQs in order, but it can be hardwired however the motherboard designer wanted to. IIRC,
the MP Tables lists all the ISA IRQs, while ACPI lists only the ones that are different from the PIC IRQ number (or
trigger / active modes).

Hi,

smoothCoder wrote:This sounds bad.
Now I have to initialize and re-map the APICs for first time in my life. So I am a bit confused. At this point is not time to me for mess with non-standard chipset stuff.

So, can I just use the devices that appears as functions on the PCI-ISA Bridge without complicating my life? These functions have IRQs and memory/IO ports etc. It would be wonderfool if I can just skip this way a lot of job. I have to save time, you know. I want to have an hobby-OS done before the apocalipse of 2012

The firmware should've already configured everything in the PCI to LPC/ISA Bridge appropriately.

smoothCoder wrote:PD: I found the datashied about ICH10. It appears to be the thing I need to read(>800 pages).

That datasheet covers a lot more than just the PCI to LPC Bridge (it also includes ethernet, SATA controllers, USB controllers, HPET, and a lot more stuff that's in the I/O Controller Hub which aren't part of the PCI to LPC Bridge itself). Mostly you only really need Chapter 13 (about 114 pages), but some of that is legacy devices (PIT, PICs, etc) that you don't need to worry about.

smoothCoder wrote:But now another question: Now can I know the model of southbridge that I have(from inside the OS, not reading the back of the laptop:)?My Host to PCI Bridge(in the virtual machine) is 82443BX, and I dont know if it use ICH2, ICH5 or 10,(in the datashied I have searched something about ICH*, but nothing) how can I know it?

Like all PCI devices, the PCI to LPC bridge has a Vendor ID and a Device ID in PCI configuration space. To find the Device ID you might need to find the "ICH10 Specification Update".

For the virtual machine, you probably want the "Intel 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator" datasheet (which includes the PCI to ISA bridge).


Cheers,

Brendan

Thank you, Brendan!

I never expected chipset stuff to be so important. Now, detecting the chipset and loading drivers(basic drivers ) for it, will be one of the first things my second stage loader will try to do.

Thanks!

I never expected chipset stuff to be so important

I don't see any reason to depend on a chipset driver here: the PCI buses and ISA bridge are properly configured upon boot and the MP/ACPI tables hold all the other information. Look at it from this way: The OS will needs to work well enough so that you can actually install the chipset driver. Hence, the BIOS makes sure you can actually do that.

Thanks, actually this was the thing I wanted to know when I wrote this post. I am now trying to automate the process of configuring the APICs regard of all of info I got in the system(MP/ACPI/PCI-scaning). Maybe in two weeks it will be functional.