long mode segment selectors

[a5498828]

long mode ignore base and limit of CS/DS/SS/ES.

why i cant load ss to 0 in ring != 0?
when cpu is in compatibility mode, it does matter. but when cpu is in long mode? does default bit somehow matters in long mode? i think long mode use always RSP (not ESP/SP like in compatibility mode).

so my question is why long modew disallow ss = 0?

[Owen]

Wrong descriptor privilege level bits perhaps?

In any case: My understanding is that the processor uses SS=0 to correctly nest/un-nest mode switches.

[a5498828]

i dont get it. retf allows ss null unless im returning to non64bit code (wich is obvious) and if im returning to ring3.

WHY?
i can load ss to null only in ring0

explain me it plz.

[gerryg400]

WHY?
i can load ss to null only in ring0

explain me it plz.

Are you asking why the AMD engineers chose to do it this way ?

Try loading a NULL selector that has an RPL that matches the DPL and CPL. That is for ring 1 use 0x01 as the NULL selector and for ring 2 use 0x02. For ring 3 you cannot load a NULL selector. Even NULL selectors have an RPL.

[a5498828]

Are you asking why the AMD engineers chose to do it this way ?

yes.
if im to understand it, i have to know what creators had in mind.

[a5498828]

when i return using iret/retf and ss is null, according to manual cpu wont load new ss.
instead it force it load null with any rpl (wich is impossible with non-null value). is this correct, or my emulator is broken? manual dont say what will be new ss after iret (and that frustrate me, it doesnt exactly say what happens, i have to test to know, everything.).

[gerryg400]

when i return using iret/retf and ss is null, according to manual cpu wont load new ss.
instead it force it load null with any rpl (wich is impossible with non-null value). is this correct, or my emulator is broken? manual dont say what will be new ss after iret (and that frustrate me, it doesnt exactly say what happens, i have to test to know, everything.).

It sounds correct to me. Read both AMD and Intel book to get more information. The AMD has a little bit more info.

manual dont say what will be new ss after iret

The SS after IRET pops from the stack. If the POPed value selector is NULL it means that the interrupt is nested.