weird 64 bit mode ......

[nikito]

Hi!
I have entered 64 bit mode.
OK.
But:
this code:

Code: Select all

xor RAX, RAX
add RAX, 48
mov byte [DS:0B8000], AL

xor RBX, RBX
add RBX, 48
mov byte [DS:0B8002], BL

xor RCX, RCX
add RCX, 48
mov byte [DS:0B8004], CL

xor RDX, RDX
add RDX, 48
mov byte [DS:0B8006], DL

Produces output : "/000"

What is going on?!?!

Thanks in advice!

[thepowersgang]

Ok,
1. That is a terrible way to load registers (use mov al, 0x30 instead)
2. What is it supposed to do? I assume print 0000.

Try using only one register and loading from that and see what happens.

[nikito]

HI, thanks to reply.

I want to print the value of the register if hopefully it is less than 10. Then adding 48 give me the ascii code for numbers.
BTW. I know this will be not an explication Why some registers works and other not, but maybe is a clue :

Using 32 bits registers alone, works as expected. Did I even entered properly in 64 bit mode?

I am trying to read the bit 10 of the MSR in ECX 0c0000080h but it not sets to report 32e mode enabled.
I make it all necessary to enter 64 bit mode, except setting up and enabling paging, because I don't need it.

Thanks.

[Owen]

I am trying to read the bit 10 of the MSR in ECX 0c0000080h but it not sets to report 32e mode enabled.
I make it all necessary to enter 64 bit mode, except setting up and enabling paging, because I don't need it.

Thanks.

But you do! Long mode requires paging. LMA will not be set and long mode will not be entered until you correctly enable PAE paging.

[nikito]

Thanks to reply, EVA 00

Then, you told me to enable and configure paging even never will use it.
I will make a search trough the Intel manual. Seems like there are things left to learn.

Ok.
Thank you very much!
I'll be back...

PD: I am back. Sory, it is EVA 01

What a mistake. I was thinking the paging is for write on disk when there are no more RAM available in the system.
Apparently the paging is core part of 32ext mode.

Thanks guys

[Solar]

"Paging" is a very bad name for two mostly unrelated concepts:

1) Virtual Addressing - where you provide a virtual address space, which is mapped to physical address space (in blocks of 4k or 4M called "pages") by means of the MMU and page tables. This is closely related to the concept of memory protection.

2) Virtual Memory - where some of your virtual pages are not mapped to physical address space at all, but rather put on the hard drive ("paged out") until you need them, so more physical address space is available for other things.

You don't have to do 2), but you need to do 1) to get into long mode, and it's a very elementary means of protecting your system against malware and broken software.

[nikito]

HI, all!

Y have done all the page structures regard the output of the e820, and now trying to modify the PG bit in CR0, the CPU restart.
I am in Protected mode, I load the CR3, with the address, active PAE bit, set the IA-32e bit in the MSR, then trying to set the PG bit it restarts.
I am trying to catch an exception but can not,

My question is, how I catch an page fault. It seams meaningless to me: While setting the PG bit, it fire an page fault, then request an ISR, but can't find ISR code, because it is in paging mode and cant calculate the physic address, because paging don't work.



Sorry, before, ask here, I fought all day with the reboot inferno.

Thanks in advance!

Niki

[gerryg400]

how I catch an page fault.

Actually I don't think you can. You're kinda in the dark. It's going to be debug by code inspection I think.

[nikito]

I read the code one and one times. Finally simplified all - just one 2MB entry paged. But still when touch the PG flag restart.
I have put the page structure at 2000h, 3000h etc, nothing.

One more question:
I have set only the bits 0 an 1 in all entries(caching theory is still too big challenge to me), and for the 2MB page entry have set the bit 7 too.
Do I have to set more bits to get it working?

thanks

[gerryg400]

Is it possible to attach your code for review?

[nikito]

Cutting a lot of lines, this is what I thing is relevant(I had to rewrite it at hand, because the develop PC have not Internet):

Code: Select all

;.....

;Reading the e820 output, I run out of available registers and use BP, after that not restore it, I need to do it?

;.....

;My stack is set up next to entering protect mode:
protect_code:
mov AX, Data_Selector
mov DS, AX
mov SS, AX
mov ESP, 090h              ;I put here random number, it seems to works whatever put here, I don't understand the stack very fine  :oops: 

;.......

cli

;........

;Here I modify some registers in order to activate SSE

mov EAX, CR4
or EAX, 600h
mov CR4, EAX
mov EAX, CR0
and EAX, 0FFFFFFFBh
or EAX, 2
mov CR0, EAX

;......

mov EAX, 2000h            ;base address for PML4
mov ECX, EAX
add ECX, 4096
mov EDX, ECX
shl EDX, 12                   ;Here I ignore upper bits of dirrection, because tables is below 1MB
or EDX, 1
or EDX, 2
mov [DS:EAX], EDX      ;DS:EAX == 0+EAX
add EAX, 4
mov EDX, 0
mov [DS:EAX], EDX
add EAX, 4
fill_PML4:
    mov dword [DS:EAX], 0
    add EAX, 4
    mov dword [DS:EAX], 0
    add EAX, 4
    cmp EAX, ECX
jne fill_PML4                  ;Here EAX keep the base for the next table

mov EDX, EAX
add EAX, 4096
mov ESI, EAX
mov ECX, EAX
shl ECX, 12
or ECX, 1
or ECX, 2
mov [DS:EDX], ECX
add EDX, 4
mov ECX, 0
mov [DS:EDX], ECX
add EDX, 4
fill_PDPT:
    mov dword [DS:EDX], 0
    add EDX, 4
    mov dword [DS:EDX], 0
    add EDX, 4
    cmp EDX, ESI
jne fill_PDPT

mov dword [DS:EDX], 83h
add EDX, 4
mov dword [DS:EDX], 0
add EDX, 4
mov EDI, 511
fill_PD:
    mov dword [DS:EDX], 0
    mov EDX, 4
    mov dword [DS:EDX], 0
    add EDX, 4
    dec EDI
    cmp EDI, 0
jne fill_PD

mov EAX, 2000h
shl EAX, 12
mov CR3, EAX

mov EAX, CR4
or EAX, 32
mov CR4, EAX

mov ECX, 0C0000080h
rdmsr
or EAX, 100h
wrmsr

;At this point work

mov EAX, CR0
or EAX, 80000000h
mov CR0, EAX                  ;Here restart

I don't know if can simplify more the code, still don't work and still don't see an error

Thanks for reading the code

Niki

[gerryg400]

Code: Select all

mov EAX, 2000h            ;base address for PML4
mov ECX, EAX
add ECX, 4096
mov EDX, ECX
shl EDX, 12                   ;Here I ignore upper bits of dirrection, because tables is below 1MB
or EDX, 1
or EDX, 2
mov [DS:EAX], EDX      ;DS:EAX == 0+EAX

What is the shl for ?

[nikito]

I know that the address to the next table begin from bit 12(21/2MB page) to the physical or logical canonical limit I forgot.
From Intel manuals.

PD:Recently deleted all SSE stuff, still not working.

[gerryg400]

Code: Select all

mov EAX, 2000h            ;base address for PML4
mov ECX, EAX         ; ecx is also 0x2000
add ECX, 4096        ; ecx is now 0x3000
mov EDX, ECX         ; edx is also 0x3000
shl EDX, 12             ; Now edx is 0x3000000 ! Is that correct ?      ;Here I ignore upper bits of dirrection, because tables is below 1MB
or EDX, 1              
or EDX, 2                ; Finally edx is 0x3000003, shouldn't it be 0x3003 ?
mov [DS:EAX], EDX      ;DS:EAX == 0+EAX

I put some comments in your code. Hope they're right.

[nikito]

; Finally edx is 0x3000003, shouldn't it be 0x3003 ?

I remember have read this in the net(000*003)
Maybe you have the right.
I will look again the intel manuals and will probe with *003.

PD:O, ****, I think I got it, it is like the address of registers in the PCI headers. There took me much time to understand that the 0 bits are part of the directions.
I will now try and will comment.

PD: Nop!
Will search some code examples to see how they do it.



PD:PD:PD:
@gerryg400
Thanks for the clue

I am now in long mode.
All 64 registers works fine.

It is really naturally aligned to 4096, And more/I now cant imagine how there can be loaded an address that is not alligned to 1000h, just like the PCI conf header registers aligned to 4 if remember fine

Thanks guys for the effort!


Last PD: I just forgot. To work cut all lines containing "shl ....." Just writing in there the address, no SHIFTs and CR3 the same.