OSDev.org

Posted: **Fri Apr 09, 2010 7:02 am**

I want to use the same Makefile for compiling a static and a dynamic version of my code. The Problem I have is, I don´t want to use the PIC code for the static library and I would like to use the advantage of makefiles, to compile only these files which need to be compiled because of some change.

This all is not that hard, but I use a depend file (output from gcc -M) for my targets and I don´t know how to change the flags for gcc and also the output filename.

So I hope you get what I want. The solution I have is using a shell script and then imitate the behavior of a makefile, but I want to try to no doing this.

Posted: **Fri Apr 09, 2010 12:42 pm**

Hi ,
I do not understand your question correctly, But what pervents you from having more than one targets ? You can have one target for building the library as a static one and the other for building it as dynamic one

.
--Thomas

Posted: **Fri Apr 09, 2010 1:00 pm**

Ok, this is one of my Makefiles:

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CFLAGS = -O2 -Wall -nostartfiles  -fno-builtin -march=i586 -I../../../src/include -I../../../../include -fno-common
LDFLAGS = -nostdlib -i
PREFIX = ../../../src/$(TYPE)/
SRCS = check.c init.c
OBJS = $(SRCS:%.c=%.o)
DEPENDFILE = .depend
VPATH = $(PREFIX)$(MOD)/
MOD = amd-k5
TYPE = cpu

.PHONY: all clean

all: $(DEPENDFILE) $(MOD).ko

$(DEPENDFILE): $(SRCS:%=$(PREFIX)$(MOD)/%)
	$(CC) -M $(SRCS:%=$(PREFIX)$(MOD)/%) $(CFLAGS) > $(DEPENDFILE)

-include $(DEPENDFILE)

$(MOD).ko: $(OBJS) Makefile
	$(LD) $(OBJS) -o $(MOD).ko $(LDFLAGS)
	cp $(MOD).ko ../
	
clean:
	-rm -f *.ko
	-rm -f *.o
	-rm -f *.s
	-rm -f $(DEPENDFILE)

The problem I have is that I need 2 object files from 1 source file with different CFLAGS (so that for the dynamic version I have "-fPIC" and for the static version I wont have it). As I include the depend file I can´t change the target or is there a way I don´t know?

Posted: **Mon Apr 12, 2010 8:18 am**

Hi ,
That's what I said , you can have two targets

.I am spolied by Visual studio,long time since I have written build scripts by hand

.Anyways , here is the plan , make 2 variables for everything you need . eg CFLAGSSHARED for shared library etc .
Let me modify your makefile and show it you (untested though !) .

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CFLAGS = -O2 -Wall -nostartfiles  -fno-builtin -march=i586 -I../../../src/include -I../../../../include -fno-common
CFLAGSSHARED = -O2 -Wall -fPIC -nostartfiles  -fno-builtin -march=i586 -I../../../src/include -I../../../../include -fno-common
LDFLAGS = -nostdlib -i
PREFIX = ../../../src/$(TYPE)/
SRCS = check.c init.c
OBJS = $(SRCS:%.c=%.o)
OBJSSHARED = $(SRCS:%.c=%s.o)
DEPENDFILE = .depend
DEPENDSHARED = .depend2
VPATH = $(PREFIX)$(MOD)/
MOD = amd-k5
TYPE = cpu

.PHONY: all clean

static: $(DEPENDFILE) $(MOD).ko

$(DEPENDFILE): $(SRCS:%=$(PREFIX)$(MOD)/%)
   $(CC) -M $(SRCS:%=$(PREFIX)$(MOD)/%) $(CFLAGS) > $(DEPENDFILE)

-include $(DEPENDFILE)

$(MOD).ko: $(OBJS) Makefile
   $(LD) $(OBJS) -o $(MOD).ko $(LDFLAGS)
   cp $(MOD).ko ../
shared: $(DEPENDSHARED) $(MOD).kp

$(DEPENDSHARED): $(SRCS:%=$(PREFIX)$(MOD)/%)
   $(CC) -M $(SRCS:%=$(PREFIX)$(MOD)/%) $(CFLAGSSHARED) > $(DEPENDSHARED)

-include $(DEPENDSHARED)

$(MOD).kp: $(OBJS) Makefile
   $(LD) $(OBJS) -o $(MOD).kp $(LDFLAGS)
   cp $(MOD).kp ../

clean:
   -rm -f *.ko

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make static

, will make the static llibrary and

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make shared

will build the shared library

.Pardon me if there is any error . I am also not so great at these things

and certainly there are more elegant ways of doing this

--Thomas

Posted: **Mon Apr 12, 2010 8:31 am**

Thanks for your help, but it wont work this way

The problem is, that CFLAGS is an environment variable which is used when you use a target just to tell the dependencies, e.g.:

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test.o: ../src/test.c ../src/include/test.h ../../include/forall.h

The make program will call gcc so (I think so):

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$(CC) $(CFLAGS) -c -o test.o ../src/test.c

And this is my problem. Even if I use grep/sed for making me 2 dependfiles out of one (to change the target filename), how can I change CFLAGS so that it 1 time compiles with "-fPIC" and 1 time without it?

So at the moment I try to read some tutorials on grep/sed to make me 2 dependfiles (with the right call to gcc and not just as I get it from gcc -M).

Posted: **Mon Apr 12, 2010 10:56 am**

So if anyone is interested on my solution, here it is:

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CC = i586-elf-gcc
LD = i586-elf-ld
CFLAGS = -O2 -Wall -nostartfiles -fno-builtin -march=i586 -I$(PREFIX)include -I../../../include -fno-common
PREFIX = ../src/
SRCS = timer.c
OBJS_STATIC = $(SRCS:%.c=%.static.o)
OBJS_SHARED = $(SRCS:%.c=%.shared.o)
VPATH = $(PREFIX)
LIBNAME = os
DEPENDFILE = .depend

.PHONY: all clean

all: $(DEPENDFILE) lib$(LIBNAME).a lib$(LIBNAME).so

$(DEPENDFILE): $(SRCS:%=$(PREFIX)%)
	$(CC) -M $(SRCS:%=$(PREFIX)%) $(CFLAGS) > $(DEPENDFILE)
	sed -e 's/\.o:/\.static.o:/' -e 's/\.h$$\|\.c$$/&\n\t\$$\(CC\) \$$\(CFLAGS\) -c -o \$$@ \$$</' $(DEPENDFILE) > $(DEPENDFILE)_static
	sed -e 's/\.o:/\.shared.o:/' -e 's/\.h$$\|\.c$$/&\n\t\$$\(CC\) \$$\(CFLAGS\) -fPIC -c -o \$$@ \$$</' $(DEPENDFILE) > $(DEPENDFILE)_shared

-include $(DEPENDFILE)_static

lib$(LIBNAME).a: $(OBJS_STATIC) Makefile
	ar rcs lib$(LIBNAME).a $(OBJS)
	cp lib$(LIBNAME).a ../../

-include $(DEPENDFILE)_shared

lib$(LIBNAME).so: $(OBJS_SHARED) Makefile
	$(LD) -shared -o lib$(LIBNAME).so $(OBJS)
	cp lib$(LIBNAME).so ../../
	
clean:
	-rm -f $(DEPENDFILE)*
	-rm -f lib$(LIBNAME).*
	-rm -f *.o
	-rm -f *.s

Now can come all the clever people to tell me the clever way

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