Some thing on PCI I dont understand...
Posted: Sun Feb 07, 2010 4:02 pm
Hi all!
I detect 4 devices on bus 0, and all they are master capable or enabled(really don't know if enabled or capable, they have the master bit in command header register set). What exactly the Bus Master stand for?
One of the devices are a Host-PCI bridge. It is almost entirely zeroed. Have I to configure the Host-PCI Bridge?
I found an CDrom device in the function 1 of the PCI-ISA bridge. The IRQ number is zero. Apparently CDrom don't use IRQ-s. Therefore I dont know how to implement the demo driver for ATAPI PIO in wiki.osdev. He need an Interrupt.
I have 2 devices with the same IRQ-s: "0xB",and the same line: INTA, on the same bus 0. They are the VGA compatible controller and the Fast ethernet controller. How this scenario work?
I have an PCI-ISA bridge and only one PCI bus. The MP table show me 2 buses: PCI and ISA. The table report I/O APIC Interrupt entries for both buses. Do this means that the IRQ-s for a device present under one of the functions of the PCI-ISA bridge will be seen by the I/O APIC as coming from ISA bus?
PD:I have a year in the programming world and it seems well and easy. The last week was my first encounter with the hardware and I'm terrified.
Thanks in advance!
I detect 4 devices on bus 0, and all they are master capable or enabled(really don't know if enabled or capable, they have the master bit in command header register set). What exactly the Bus Master stand for?
One of the devices are a Host-PCI bridge. It is almost entirely zeroed. Have I to configure the Host-PCI Bridge?
I found an CDrom device in the function 1 of the PCI-ISA bridge. The IRQ number is zero. Apparently CDrom don't use IRQ-s. Therefore I dont know how to implement the demo driver for ATAPI PIO in wiki.osdev. He need an Interrupt.
I have 2 devices with the same IRQ-s: "0xB",and the same line: INTA, on the same bus 0. They are the VGA compatible controller and the Fast ethernet controller. How this scenario work?
I have an PCI-ISA bridge and only one PCI bus. The MP table show me 2 buses: PCI and ISA. The table report I/O APIC Interrupt entries for both buses. Do this means that the IRQ-s for a device present under one of the functions of the PCI-ISA bridge will be seen by the I/O APIC as coming from ISA bus?
PD:I have a year in the programming world and it seems well and easy. The last week was my first encounter with the hardware and I'm terrified.
Thanks in advance!