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how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 12:54 am
by blackoil
Hi,

kernel PD is 1024 * 4 = 4096bytes
kernel PT is 1048576 * 4 = 4MB
so kernel can address 4GB space

if each application can address virtually 2GB, whitch starts @ 0x00000000
then should I reserve 2KB + 2MB space for its virtual addressing?

if each application starts at arbitary address that the paging allocator assigned
then may I save 2KB + 2MB space?

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 2:54 am
by AJ
Hi,

There are lots of ways of doing this - let me outline a fairly popular one involvng a higher-half kernel:

Map the last entry in the PD to itself. This means that the last 4MiB of virtual RAM contains the page directory and all page tables for the current task space. Create page tables for your kernel space (for arguments sake, if your kernel is at 0xC0000000, this means you need 1MiB of physical RAM for kernel-level page tables) but leave the lower 3GiB of memory unmapped.

As you create a new task, create a new PD. The top KiB of this new PD needs to be a copy of your existng PD and the bottom 3K will be unmapped. The very last entry of your new PD should point to the new PD (physical address!) you have just created.

This means that each task has the bottom 3GiB of memory to play with and this part of each PD will be task-specific. It also means that whatever task you switch to, kernel space is mapped in exactly the same way. You simply lose 4MiB of virtual address space for the PD mapping.

Cheers,
Adam

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 7:28 am
by blackoil
Well, It a good tricky solution. Does it have a name? I need to google it for more details.

Each application has 3GiB space, its PD 3KiB + PT 3MiB fits in 4MiB.
When application is to be run, kernel allocates a 4MiB page with CR3 loaded.

So does each application still cost 4MiB physical memory for its PD+PT?

And why the app PD[1023] should be PD addr itself?
Does it be used by the kernel for task switch?

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 8:50 am
by Combuster
you don't need to map (and allocate) any pagetables until you need them. Best case you only need 8k: one PD, one PT for your code, and reusing the kernel's PTs. Then when you expand you can indeed allocate extra pagetables as necessary.

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 10:17 am
by AJ
Using the above method, 1MiB is used for mapping kernel space. You map these (empty) page tables in before launching your first process which ensures that all processes see the same kernel space. This 1MiB therefore only happens once as it is shared between all processes.

As combuster says, the user space is not mapped in until you use it, so there is the potential for each process to require an additional 3MiB. [edit]I repeated too much of Combuster's answer![/edit]

Cheers,
Adam

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 10:26 am
by blackoil
ok. Just need to set up a 4MiB page table for global usage.
Kernel & app PD link to it.

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 10:31 am
by Combuster
*waits for the epic fail*

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 10:50 am
by AJ
Combuster wrote:*waits for the epic fail*
Have more faith - he may just have phrased that last reply badly [-o<

Re: how to design a paging manager with multitask support?

Posted: Thu Nov 06, 2008 8:45 pm
by blackoil
I think I got your meaning.

I set up a 4MiB page tables, the last 1MiB is for kernel only.

When a app starts, I pick up a page for its PD, another page for its PT, then some pages for the code itself. As the app access extra memory, I continue to allocate more pages for its PT, and set PD+PT link up.

Re: how to design a paging manager with multitask support?

Posted: Fri Nov 07, 2008 2:39 am
by AJ
Let me just clarify - this may just be a grammatical difference!

At kernel startup (assuming a kernel at 0xC0000000):
1) Create a PD for the kernel where the last entry points to the PD itself.
2) Create PT's and the associated entries in the page directory for the last 1GiB of RAM (this will "waste" 1MiB of physical RAM for the page tables).
3) Good practice - zero the new PT's and the lower 3KiB of the PD.

When a process starts (assuming a kernel at 0xC0000000):
1) Create a new PD - copy the top 1k of the current PD to the new PD.
2) Zero the rest of the new PD.
3) Change the top entry of the new PD to point to itself (so the top 4MiB of RAM always point to the page tables of the current PD).

Now it gets a bit confusing. There is currently another forum question relating to this - how do you map in the user task? It wil obviously use the user-space portion (lower 3GiB) of your new page tables, but do you map space in to *both* task spaces in order to load the stack and executable or not? I just create a new stack for the new task and switch to the new task in kernel mode. The user binary is then loaded in to the new task space as required. This requires some thought and planning!

Cheers,
Adam

Re: how to design a paging manager with multitask support?

Posted: Fri Nov 07, 2008 9:18 am
by blackoil
Hi, AJ

I have a basic plan, but haven't written any codes to prove it yet.

Reserve 1MiB physical memory somewhere for kernel.

When a app starts,
Pick up a page in page_inuse_bitmap for the app PD, the app PD last 1K is marked as present system page, the first 3K is non-present user page.
Pick up pages in page_inuse_bitmap for the app code, then its PD&PT mapping.
Pick up pages in page_inuse_bitmap for the app data, then its PD&PT mapping.
Pick up pages in page_inuse_bitmap for the app stack, then its PD&PT mapping.

page allocation for PT and its mapping to PD are done according to what kernel PageAllocator returned & what address,size specified in app's ELF.

The kernel keep track of how many pages the app occupied (PD PT code data stack).