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and MMreg are mixed with FPreg

I'm not sure what you mean. If you want to use XMM registers, just go ahead.

I mean use XMM register set for SIMD only

Hi,

blackoil wrote:I mean use XMM register set for SIMD only

The XMM registers are used for SIMD (SSE) only.

Do you mean using MMX registers for SIMD only, instead of having them aliased to FPU registers?

In this case, would you suggest removing the FPU completely (and having no non-SIMD floating point support at all), or would you add separate MMX registers so that you could use MMX and FPU at the same time (and so that context switching takes longer)? In this case (separate MMX and FPU registers), it'd be better to just use SSE instead of MMX if you also need the FPU...

Of course this assumes we're talking about general purpose CPUs. I'd like to see minimal CPUs for embedded systems (e.g. Atom without FPU, MMX or SSE); and I'd like to see "mixed core" (e.g. two full featured cores, plus 4 minimal "long mode only" cores without FPU, MMX or SSE in the same chip).


Cheers,

Brendan

Hi Brendan,

MMX and FP share the same registers set, and 80bit precison max.
In procedure with 2 slots operation, MMX or XMM is ok, but XMM is seperated set, doesn't need to transition between FP and MMX state. So I think MMX will be replaced with more dedicated XMM soon. And I like CELL/BE architecture, but it's not for common PC.

Define 'replaced'. Production software probably rarely uses MMX at all anymore, if ever. The CPU implementation only exists for backwards compatibility. So effectively SSE has already replaced MMX.