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When the CPU generates an I/O address,how does a device know it is being addressed?I mean,what & how association is made between the CPU generated number(address) & a device?Where is this association stored for future use?

A few legacy devices have hardcoded "traditional" IO port addresses that can be found in the wiki articles for those particular devices, or in RBIL.

Other devices have internal registers that allow the driver to choose from a very short list of "legal" IO ports for that device. The setup procedure for those is device-specific.

PCI devices usually have their IO port addresses set by the BIOS during bootup. Their IO addresses are stored in the BARs in their PCI Configuration Spaces.

bewing wrote:A few legacy devices have hardcoded "traditional" IO port addresses that can be found in the wiki articles for those particular devices, or in RBIL.

Other devices have internal registers that allow the driver to choose from a very short list of "legal" IO ports for that device. The setup procedure for those is device-specific.

PCI devices usually have their IO port addresses set by the BIOS during bootup. Their IO addresses are stored in the BARs in their PCI Configuration Spaces.

But my question remains-how does the CPU know which is the intended device?Is the device address specified in the instruction?

Hi,

abhishekmaharana wrote:But my question remains-how does the CPU know which is the intended device?Is the device address specified in the instruction?

The CPU doesn't know or care. It says "I want to read from I/O port 0x1234" on the front-side bus and waits for a response. Everything else on the front-side bus checks to see if it should respond.

Typically, the I/O hub (or PCI host controller) would recognize the I/O port as something it should forward to the PCI bus, so it does, and everything on the PCI bus will check to see if it's something it should respond to. This means an actual device on the PCI bus might respond and send it's response to the PCI host controller (via. the PCI bus) and the PCI host controller would forward the response to the CPU (via. the FSB).

It's also possible for the request to be forwarded through a PCI to PCI bridge or through a PCI to LPC bridge, and it's possible for a request to pass through many different buses until something actually responds (instead of forwarding it). Still, the basic idea is the same - any device could respond to any request and only the device itself really knows what it will respond to (but devices are designed to only respond when they should, depending on device type, standards, etc).


Cheers,

Brendan