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I'm a little confused about stack alignment. I had always been aligning the stack so that (ESP mod 4) = 0 or (SP mod 2) = 0, assuming that I was aligning it on a dword boundary, like the Intel docs say it should be. Then I noticed that the docs referred to values of SP at 1, 3, 5, 7, etc, implying that (SP mod 2) should be 1 and (ESP mod 4) should be 3. In looking at other people's code, I've seen it both ways. Does the stack store data differently than normal (ie 'mov [ss:0x3] eax' would store eax somewhere other than bytes 0x3 through 0x6)? If it does, that seems to have all kinds of weird implications. For example would this:

mov eax esp
mov ebx [eax]

store something different in ebx than this:

mov ebx [esp]

If someone could please explain this to me, I would really appreciate it, because it's making my brain hurt, because it makes no sense.

It's not going to give you any different results, but it will be slower if (ESP mod 4) != 0. It's the same as any unaligned memory access. The CPU can read and write longs on 4 byte aligned addresses, shorts on 2-byte addresses, and words anywhere. To read an unaligned long, the CPU must do two reads and discard four of the eight bytes it gets. Having data (including stacks) minimizes this.