OSDev.org

I have seen many references on the web indicating that on 'recent' Intel chipsets, DMA activity is snooped and the CPU cache will remain coherent thus allowing the use of cached memory for DMA activity.
I am writing an IDE driver for an embedded system using a Pentium-M and 855 family chipset. Obviously, application performance is increased if the memory used by DMA transfers to/from IDE is write-back (the DMA is not faster but use of the memory by the app is faster). If I set the memory to write-back and start a DMA transfer from a drive to the memory, I see one FSB transaction per cache-line worth of data (via the Intel performance counters). I assume these are snoop cycles. I see similar activity if the CPU writes to the memory and then commands the data to be written to the drive. In all test cases using write-back memory the data stays coherent with the processor cache.
My problem is that I cannot find any Intel documentation that guarantees or even discusses the coherency of the processor cache in the presence of DMA activity. Can anyone point me in the right direction?
thanks.

did you try the chipset documentation? (in case you didnt know, intel provides complete documentation for everything they make, free of charge)
downloadable from the developers website:
http://developer.intel.com
specifically the 855 chipset:
http://developer.intel.com/products/chi ... /index.htm

JAAman,
Thanks for the reply.
Yes, I have searched the chipset and processor datasheets, the Pentium Programmers Manuals, the Optimization Guide, 855 BIOS Developers Manual, the Intel web site and Google. I can find much documentation about when AGP accesses get snooped and not snooped but not PCI DMA transactions. After reading the docs you are left with a vague implication that it is done but there is nothing specific.
It is odd and frustrating.

That lack of availability of the info makes me suspect that it might be part of the (unbearably hard to find) official PCI documentation?

Hi,

rollout wrote:After reading the docs you are left with a vague implication that it is done but there is nothing specific.

I'd assume that (as far as cache coherence and the FSB is concerned) there's no real difference between bus master activity and CPU activity. For example, CPUA would get snoop traffic which may have come from the northbridge/PCI or from another CPU.

With this in mind I'd be looking for SMP cache coherency protocols, rather than anything specifically related to bus mastering...


Cheers,

Brendan

bewing - thank you. I do have access to the PCI specs and it is not specifically covered there.
Brendan - I think you are on the right track. For example, the MESI cache protocol would seem to cover my question. However, all Intel docs I have read refer to coherency in a multi-processor environment. If they were a little more vague and talked about coherency with another agent and not specifically with another CPU, I'd be covered.
I'm thinking this might be covered in books published by Intel Press and not otherwise available on their web site?

Hi,

rollout wrote:Brendan - I think you are on the right track. For example, the MESI cache protocol would seem to cover my question. However, all Intel docs I have read refer to coherency in a multi-processor environment. If they were a little more vague and talked about coherency with another agent and not specifically with another CPU, I'd be covered.
I'm thinking this might be covered in books published by Intel Press and not otherwise available on their web site?

The information might be in something published by Intel Press, but (given that this information is only normally needed by chipset designers and Intel engineers) it might be information that Intel only let licensed partners have.

Is there some reason that you need to know more than "yes, it works"?

If it didn't work, then it'd break compatability with every other "PC compatible" computer and seriously annoy developers for all operating systems; and I'd guess Intel are the only ones who can provide something like a written guarantee (which they generally don't do, especially for "medical, life saving, or life sustaining applications") .


Cheers,

Brendan

Brendan,
I would guess that many developers would make their DMA memory uncached and leave it at that. So I'm not sure how much stuff would break if it didn't work. And there's history of errata concerning coherency with similar accesses via AGP not working correctly. So perhaps driver developers want to play it safe.
Unfortunately, I do need hard data to justify this decision. Application performance is also a concern so I don't want to concede to using uncached if I don't have to.
Your input has been appreciated. Thank you.