Themis Slice is a blade motherboard with 3 CPU sockets. According to Themis 3 sockets is faster than 4 sockets, because there is a direct connection between all sockets.
IMO if the CPU vendor create chipset / multicores CPU with configurable / programmable data links between sockets / core, this will solve the latency problem, similar to the "dead" transputer CPUs.
The operating system / applications can change the data links configuration between sockets / cores during runtime.
Is there any present chipset / multicores CPU with configurable /programmable data links?
From Inquirer:
"Why would you want three sockets rather than four? Easy, latency. Any CPU in a 3S system is one hop away from any other CPU. In a 4S system, you can be two hops away. This adds latency, and more importantly, you take a big hit on cache coherency latency. This kills performance. Because of this, a 3S machine may end up faster than a 4S under some workloads. Given an equal CPU count, a cluster of 3S machines will be faster than 4S machines. You only pay for it in density and the odd looks your co-admins give you when you tell then you have 3S machines."
OS That Support Configurable Data Links Between CPU
Hi,
Communication between CPU #A and CPU #C involves 2 hops. Latest rumours say the newest AMD CPUs will have 4 HT links, but you won't be able to use all of those links until AMD introduce a new socket (not enough pins on the corrent socket).
Cheers,
Brendan
At least one link in one CPU needs to be used for I/O...Candy wrote:That is assuming you have 2-link cpu's. AMD64 cpu's have 3 links, so 4 would be optimal (iirc that is - you could use one link per cpu for something else, after which 3 would be better). What's this doing in OS design & theory?
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B-A-IO
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C-DCheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.