OSDev.org

I have read in some places that the memory must be aligned according to its size, and so they don't impact performance:

Arbitrary-size structures: 16-byte boundary (if used with SIMD instructions)
Single bytes: Anywhere
WORDs: Word-aligned
DWORDs: DWORD-aligned
QWORDs: QWORD-aligned
Code: Aligned to 2-byte (RM), 4-byte (PM) or 8-byte (64bit)


If so, it seems more comfortable, less space-wasting and an addition to the simple recommendation of always align to platform register-width.

~ wrote:I have read in some places that the memory must be aligned according to its size, and so they don't impact performance:

Arbitrary-size structures: 16-byte boundary (if used with SIMD instructions)
Single bytes: Anywhere
WORDs: Word-aligned
DWORDs: DWORD-aligned
QWORDs: QWORD-aligned
Code: Aligned to 2-byte (RM), 4-byte (PM) or 8-byte (64bit)


If so, it seems more comfortable, less space-wasting and an addition to the simple recommendation of always align to platform register-width.

For higher performance (in some cases !) use cache line alignment for some bits of code.