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Thanks
Data transfer from MEM -> SPI

1) i understand that dwc->chan.chan_id is 0, because i can choose 0 to 7 channels, each DMA has 8 channels,, am i right ?... i am setting up all Channel 0 registers..

2) What should be src_id = dwc->dws.src_id;?

case DMA_MEM_TO_DEV:
dst_id = dwc->chan.chan_id;
src_id = dwc->dws.src_id;

Thanks
Ravi

ravi wrote: ↑Mon Jul 29, 2024 12:58 pm1) i understand that dwc->chan.chan_id is 0, because i can choose 0 to 7 channels, each DMA has 8 channels,, am i right ?... i am setting up all Channel 0 registers..

Yes, that's correct.

ravi wrote: ↑Mon Jul 29, 2024 12:58 pm2) What should be src_id = dwc->dws.src_id;?

I think Linux uses 0, but it probably doesn't matter. Hardware handshaking is only used for peripherals, not memory. (And peripherals are connected through the crossbar, so maybe the IDs in CFG_HI aren't used at all...)

Thanks

finally i was able transmit couple of bytes from main memory -> PSE DMA2 -> PSE SPI,

thanks
Ravi

hello Octocontrabass,

i think PSE SPI FIFO width is max 16bit, when i am operating in 8bit mode and do DMA receive i get 00 01, 00 02, what i mean to say is DMA should asked to fetch chucks of 16bit, is this true?

1) i Have already 15 bytes of data in in 15 different SPI FIFO location(0x1, 0x2...0xf)
2) Source Transfer width = Destination Transfer width = Source message size = Destination message size =1 and DMARDLR =0;
3) when i set Block transfer size = 1, and do a DMA receive only 0x1 is received,,, this i understand
4) when i set Block transfer size = 2, and do a DMA receive 0x0001(2 bytes received, including dummy byte form 16bit FIFO),,,
5) when i set Block transfer size = 3, and do a DMA receive 0x0001(2 bytes received),,, this i do not understand
6) when i set Block transfer size = 4, and do a DMA receive 0x00020001(4 bytes received),,,
7) when i set Block transfer size = 5, and do a DMA receive 0x00020001(4 bytes received),,, this i do not understand
when i set Block transfer size = 6, and do a DMA receive 0x00020001(4 bytes received),,, this i do not understand
9) when i set Block transfer size = 7, and do a DMA receive 0x00020001(4 bytes received),,, this i do not understand
10) when i set Block transfer size = 8, and do a DMA receive 0x00020001(4 bytes received),,, this i do not understand
11) when i set Block transfer size = 8, but change Source message size = Destination message size =2 and do a DMA receive 0x0004000300020001(8 bytes received),,, this i do not understand
12) when i set Block transfer size = 6, but change Source message size = Destination message size =2 and do a DMA receive 0x0001(2 bytes received),,, this i do not understand

i am little bit confused here
my understanding is DMA is


update:
in different test, even when DMARDLR is set to 5, DMA transfer is triggered even if SPI controller has received a single byte

ravi wrote: ↑Tue Jul 30, 2024 11:42 pmi think PSE SPI FIFO width is max 16bit, when i am operating in 8bit mode and do DMA receive i get 00 01, 00 02, what i mean to say is DMA should asked to fetch chucks of 16bit, is this true?

If you're operating in 8-bit mode, you can program DMA to fetch 1 byte (SRC_TR_WIDTH = 0). I think 4 bytes (SRC_TR_WIDTH = 2) will also work, although it might not be useful.

ravi wrote: ↑Tue Jul 30, 2024 11:42 pmmy understanding is DMA is
Block Transfer is total number of bytes DMA has to transfer, so for example DMA has to transfer 6bytes with each burst = 1 byte.... where am i missing the point here

If TR_WIDTH is 1, the transfer width is 2 bytes. If MSIZE is also 1, the burst length is 2 transfers, which is 4 bytes. I'm not sure why you receive 4 bytes instead of 6, maybe that's why Linux always sets MSIZE=0 for MMIO...

ravi wrote: ↑Tue Jul 30, 2024 11:42 pmin different test, even when DMARDLR is set to 5, DMA transfer is triggered even if SPI controller has received a single byte

Maybe the SPI controller is trying to empty the RX FIFO when it's done receiving data?

oh Great! yeah i had read that in 636112 in page 427,, but when i saw its description in the registers, it confused out of me and forgot about it

Slowly its coming together now,,,,,,(my confusion is cleared about burst size, width and block size,, i think so )

new test scenario:

when bock size is 6 and message size is set to 2 (2^2 = 4) and width is 0(2^0 =1), so 4 bytes gets transferred in the first burst

so second burst should happen for 2 bytes,, i am not sure why this second burst is not happing because, DMARDLR =1 and original FIFO count was 15 out of which DMA has popped out 4 bytes so FFIO count is now 11 still > DMARDLR, SPI controller should initiate the second burst..... this not is not happing

Thanks
Ravi

Unfortunately I'm not sure what's wrong. It sounds like that should work.

I noticed Linux sets SRC_MSIZE to 0 (2^0 = 1) to prevent bursts with MMIO, but I don't know if it's a workaround for a problem like what you're seeing or just the Linux programmer being lazy. I didn't see Linux doing anything else strange, but the DMA code is spread across several files, so I might have missed something.

You may have better luck asking your contact at Intel. (...Assuming they didn't get laid off.)

Thanks, i am working on it

i tried with SRC_MSIZE =0 , when i do this DMA transfers only 1 byte and probably i think its waiting for the second burst to initiate

i had already asked Intel help for DMA support a month ago, still waiting.......

have you noticed, Status register and its bits for PSE DMA controller, in the data sheet,, i am trying to find but not getting it


thanks
Ravi

The only status registers I can find are the ones that report interrupt status. DMA may halt if it's waiting for you to acknowledge an interrupt.

It's not really a status register, but you can read BLOCK_TS to see how many read requests have been issued to the SPI controller.

Thanks Every thing is working now, just rewrote the code from scratch,,,

now on to doing list method, i think this is the method that will us circumvent the mmio delays

ravi

Hello Octocontrabass ,

LL Based transfer is also working,, but not what i expected(i think my thought processes was not accurate)

The Scenario is like this:

i have 2 commands each followed only few bytes of data, they required 2 different transaction on SPI bus ie ( CS =0 ->Cmd1 -> Data1->CS =1 and CS =0->Cmd2->Data2->CS=1)
initially i had imagined that i will populate 2 lists with each command, and start the DMA transfer(i was hoping by low water marking the FIFO's CS will be de- asserted in-between block transfers)

do you have any thoughts ?

unfortunately PSE SPI donot have software control chip select otherwise i would have tried to do CS via DMA itself

Linked lists are for scatter/gather DMA, so you can use a buffer that isn't in physically contiguous memory. They're not supposed to insert any breaks or delays.

PCH SPI/DMA is very similar to PSE SPI/DMA, except PCH SPI has manual CS control. Maybe you can adapt your code for PCH now that you've gotten PSE to work.

yeah working on that,

but i think it may not succeed, i am sure that i can do CS and immediately put data into FIFO and hardware will take care of,, but de activating CS i will have to do only when the last bit is shifted out on the BUS,,,, not sure what will happen when you deactivate CS when data still is being sent out on BUS..

May be i will i try de activating CS with SPI interrupts(but there is huge interrupt latency in micro seconds(5-15-20) that i have noticed before ). i will see what i ca do to make it work


Thanks
Ravi

Hello Octocontrabass,

i got PCH SPI DMA controller also working, with LL

I did the 1) CS via DMA -> 2) Data Via DMA-> 3) inserted a DMA delay(by copying know data into scratch pad registers)-> 4)deselected the CS via DMA

tried with Hardware control CS also it also works...

but probably of little use to us, since there is no deterministic way of the determining the delay count in step 3)

still exploring options
Ravi

ravi wrote: ↑Wed May 08, 2024 2:15 pm Hello Octocontrabass

I am trying to use PSE SPI1, RDC-614110, Intel ATom ELkhart lake

everything works fine

1) i check Status before putting anything in the Buffer (i.e waiting for TX FIFO to be 0, RX fifo to be 0 and device not busy)
2) CS asserts when the data is put in the FIFO
3) CS de asserts when FIFO is empty

occasionally every few thousand samples, what is happens is for example if the command is 8 byte wide , 6 bytes are transmitted under one sequence (i.e CS active-> data on the bus-> CS de-active) and 2 bytes are transmitted in separate sequence, this is creating lot of [problems(interrupts are disabled)

Thanks

hello Octocontrabass , i am not able to get past this problem, it happens both in PCH and PSE SPI, even when done with DMA,,, i checked if SMI are happing in-between using MSR 0x34, but the count remains to be constant