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Brendan wrote:Logical destinations are different. The basic idea is that it sends the IPI to each CPU where "( DFR & LDR & IPI_destination != 0) && (~DFR & LDR == ~DFR & IPI_destination)". For xAPIC, by carefully choosing how you use bits in the LDR you can do some fairly powerful things.

OK, so I set DFR to FF and LDR to 01, and at first it actually seemed like it worked. The keyboard ISR would always happen on core 4 when the system was idle (OK, I suppose, since all cores had the same priority). The problems start when the system become loaded. Now ISRs do happen on different cores alright, but the keyboard ISR sometimes emits two, three and even four characters for a single key-press. Are there some special considerations when ISRs are running in lowest priority mode? The keyboard ISR is atypical in that it does much of its work in the ISR, while other ISRs typically only signal completion that wakeups a server thread.

EDIT: Replacing cli/sti with a spinlock actually solves this issue.