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ravi wrote: ↑Sat Nov 23, 2024 11:00 pmi am bit confused about this section, what does this control(i am not getting a clear picture, i thought PHY had PCS)

I guess with SGMII part of the PCS is integrated into the MAC?

ravi wrote: ↑Sat Nov 23, 2024 11:00 pmhow to access these registers they all say Port Numbers and dev id

Use the MAC_MDIO_ADDRESS and MAC_MDIO_DATA registers.

ravi wrote: ↑Sat Nov 23, 2024 11:00 pmwhy all the registers are saying clause 45

You need MAC_MDIO_ADDRESS.C45E = 1 to access those registers.

Hello Octocontrabass,


"why all the registers are saying clause 45",, what i mean to ask was,, what if i am using clause 22, are these registers valid?..... if i understand what you are trying to tell is while i am accessing this registers i should use clause 45,,am i right?

i thought i understood little about DMA->MTL->MAC, but i think i have to read lot more, but not getting relevant material about this particular implementation


Thanks
Ravi

ravi wrote: ↑Sun Nov 24, 2024 10:00 pmwhat if i am using clause 22, are these registers valid?

If you're using Clause 22, you can't directly access Clause 45 registers. You can indirectly access Clause 45 registers through Clause 22 register 13 and register 14, if your hardware supports those registers.

ravi wrote: ↑Sun Nov 24, 2024 10:00 pm..... if i understand what you are trying to tell is while i am accessing this registers i should use clause 45,,am i right?

Yes.

ravi wrote: ↑Sun Nov 24, 2024 10:00 pmi thought i understood little about DMA->MTL->MAC, but i think i have to read lot more, but not getting relevant material about this particular implementation

The MII/MDIO registers are standard. You can read 802.3 clause 45 to learn more about them.