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A lot of it applies, but the specifics for setting up AArch64 paging are different. In AArch64, page tables have at least three levels, and the table at each level will fill one whole page (except the top level, which may be smaller). If you're still using 4kB pages, your page tables will have at least four levels.

If you've set up paging on x64 before, this will all look very familiar.

Here's a link to a manual that covers AArch64 paging.

Hi. I think I will do so because it seem like I will be able to be faster.

Hi. So which memory model do I use? Application, System, or Virtual Memory?

I'm not sure what you're asking. The ARM memory model is part of the ARM architecture, you can't not use it.

If you're looking for information about the page tables, that's covered in chapter D5, "The AArch64 Virtual Memory System Architecture".

Hi. This is a little side question. How do I fix the self test for gcc 7.1.0? It gives me the error "nul: invalid argument". How do I fix this?

You'll have to explain in more detail what you're doing when you get that error.

Octocontrabas wrote: If you're still using 4kB pages, your page tables will have at least four levels.

not necessarily. if you don't need all the 49 bit address space (both parts combined), you can shrink one level, by appropriate setting those SZ fields and making TTBRx point to the level 1 page table. then you have 512GB+512GB address space, which is not that small, but you have 3-level translation. I do exactly this.