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Xardfir wrote: Hiya,
I was just wondering (as I don't recall it having being mentioned) what type of memory achitecture (Candy) you have in mind - 'Havard' or 'classic Neumann'?

I'm thinking that if you're taking an FPGA route, the amount of external pins available might not initially encourage having two seperate address/data busses (one for code, one for data) but the 68k architecture IIRC had the ability to use 4Gbytes of code and 4GBytes of data, with each address space accessed dependant on the type of cycle. Kind of like a 33rd address bit that is set or reset on a 'code access cycle' or 'data read/write cycle'.

A single buss (keeping it simple) could be used to start with, whilst allowing for a full Havard system (separate caches, multiple busses) later on.
Of course the question would then arise:
"How many address bits to dedicate to each of the code / data address spaces?".

I think von Neumann, since I consider it better for multiple purposes. I like hacking for instance, and it's hard to use a couple of my hacks if you can't access instruction memory. The only real advantage I can see is being able to get twice the performance.

When I'll design a high performance processor I'll use multiple instruction and data buses for higher performance. For this one, it's way not worth it. Especially since the number of output pins increase linearly with the complexity of soldering it (the 144 pin version cyclone I's are TQFP, which is very hard to solder, the 208 pin ones are PQFP, which is even harder, and the ones above that are BGA or FBGA, which is plain impossible for me (I can't get under the chip to solder and I don't have a chip oven). Also, BGA/FBGA require a 4/6 layer board since you simply can't stuff that many signal channels beside each other with current board design techniques. The PQFP lines have to be 10 mil wide which is quite near the limits of current board makers and BGA only increases that. Also, a dual side board I can create at home, 4/6 requires ordering at prices of 200 (300 for 6-layer) euro and up for a single board, let alone not being sure I can solder it. 2-layer comes for only 50 euros for a similar board, or around 100-200 including the kit to do it myself, so subsequent boards will be 3,50 + toner cost (which is probably around 50c for proper darkness) + sheet cost (around a euro for a laser-transparency sheet or for a photo-paper-sheet).

I tend to simpler designs at the moment, I'm doing this just for the kicks of doing it.

Note to people reading this like "I would do that, but I really don't have money for it", Altera has free software that you can use for FPGA based design. It only works with their cheaper models and it (iirc) requires a web connection, but you can at least learn VHDL or Verilog that way and you can practice with how it works (I think a simple simulator is integrated, although I can't vow for the free version). You can probably code most of the design before testing on real hardware, which is also available from them (development kits or plain chips, if you're adventurous enough to want to try to create your own board - I know I am).

Altera site: www.altera.com. Afaik it's also for Linux.

Note, yes I know, they do vendor-lock-in. You can also try Xilinx (www.xilinx.com) but I can't get their software to work. They do have cheaper kits so they might be more fit for hobby purposes (yes, I'm a hypocrit).

Ok, update for Kemp:

I've been looking at PIC microchips for doing some funny stuff around the house (making led lighting in full-color etc, just frivolous things) and I've found out that most of those PIC's are 14-bit. They have 14-bit instructions and use a 14-bit flash memory for instructions. Since they're a Harvard architecture, the data is in an 8-bit memory. Still, it's nice to know. Oh, and they come in packages up to 8k flash (which then uses 13 of those bits for address).

Enjoy reading about them. Try searching for 16F628 for a specific one of them that's pretty popular.

Oh yes, PICs, I had a phase of playing around with them a few years ago. I'll read up on how they've come along since then.

I've pretty much settled on being fully 32 bit though, if the external electronics doesn't want the extra lines then it can just not use them. Plus I still have the option of doing a cut-down version if I want with the extra lines fixed to 0.

A very interesting topic....one that I've dug into for many years now. If my intrusion as a board-newbie doesn't offend, here are a few notes that might be of some small value...

1) uCode vs. 'hard' logic:

I think you might be missing the fact that, in FPGA, "hard logic" is generally designed in -software-. I.e., you are simply writing equations in VHDL. Thus, changing the "hard logic" later is not much different or more difficult than rewriting uCode. Also, although many FPGA's have mini-blocks of RAM built into them these days; there is not that much, there are speed penalties involved with its use, and the more RAM there is, the less logic there is (on the same size/cost chip).

The bottom-line is that, for CPU-design in FPGA's, the advantage lies on the side of "hard logic" I think. Such a CPU would be much faster, and fit in a smaller/cheaper part.


2) The brief back-and-forth in this thread regarding "risc vs cisc", boxes the issue to only 2 choices. There are also Stack-machines and data-flow CPU's; among other structures.

Of course cisc-v-risc is not a directly comparable argument to register-v-stack; but I hope my point is still valid....i.e. look outside the usual binary argument...there are other ideas out there....


3) Stack machines seem to consistently outperform register-based machines...by quite a large factor. And if you enjoy elegant engineering, you might find them very much to your taste. They are extremely efficient on a gates-per-function and power-per-instruction basis.

Koopman's page is a good start....

http://www.ece.cmu.edu/~koopman/stack.html

Also, I believe it is Bernd Paysan (sp?) who has designed several interesting stack-machine CPU's; including a quad-core chip that looks like it'd be VERY fast...

A last note on the CPU-design subject:

One aspect of it which has always fascinated me is the -simplest- possible CPU's. In the past, I've built several using nothing but a 22V10 and an EPROM (glorified state-machine with table-lookup for ALU etc.). It's a mind-sharpening challenge to work out how to implement an "instruction set" in VERY few bits... ;D

Anyway, on this subject, there is a paper floating around the web about a complete 8-bit CPU implemented in nothing but a 32-cell PLD !! That's pretty freaking amazing...

Sorry I don't have link, just the paper itself on my HD...but here is title/author/etc...

A minimal 8-Bit CPU in a 32 Macrocell CLPD.
Tim B?oscke, [email protected]
February 17, 2002


In more general CPU/VLSI design area....

This man's page is an interesting collection of notes, quotes, and links; regarding CPU/VLSI/FPGA design...

http://rdrop.com/~cary/html/vlsi.html


This paper on the "ultimate RISC" is an interesting read (sorry, no link...i have the paper itself on HD, but no bookmark)....

The Ultimate RISC
Part of the Computer Architecture On-Line Collection
by Douglas W. Jones, THE UNIVERSITY OF IOWA


I realize that CPU-design is not the main thrust of this board; but I did enjoy this thread, and hope these small notes add to it.

dozer

This wikipedia page:
http://en.wikipedia.org/wiki/OISC

gives the link to the Douglas Jones paper (which looks very interesting):
http://www.cs.uiowa.edu/~jones/arch/risc