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ravi wrote:clock gating is disabled(ie. set to Hw_clk)

Doesn't that mean hardware controls clock gating? Try using "force on" or "force off" and see what happens.

The PSE SPI f_input is 100MHz, but I don't know if it's the same for PCH SPI. Firmware might be able to change f_input for PCH SPI.

thanks i will try

Tried not effect,

Force on, no signal, Force Off works the same way(same frequency)

i tired with PSE SPI,, i am able to get the desired min to max Clock frequency, as per the give calculation,

not sure what is issue with PCH


Thanks
Ravi

I didn't see anything in the datasheets that would explain the PCH behavior. You might have to ask Intel directly.

OctocontrabasS

i have asked some time back yet to receive response from Intel


Thanks
Ravi

Hello Octocontrabass

I am trying to use PSE SPI1, RDC-614110, Intel ATom ELkhart lake

everything works fine

1) i check Status before putting anything in the Buffer (i.e waiting for TX FIFO to be 0, RX fifo to be 0 and device not busy)
2) CS asserts when the data is put in the FIFO
3) CS de asserts when FIFO is empty

occasionally every few thousand samples, what is happens is for example if the command is 8 byte wide , 6 bytes are transmitted under one sequence (i.e CS active-> data on the bus-> CS de-active) and 2 bytes are transmitted in separate sequence, this is creating lot of [problems(interrupts are disabled)

Thanks

ravi wrote:(interrupts are disabled)

You can't disable SMI.

Have you tried using DMA? SMI shouldn't interfere with DMA transfers.

Hello Octocontrabass

Can an SMI interrupt when in protected mode?

Evaluating Use of DMA/Interrupts


Thanks
Ravi

SMI can interrupt at any time in any mode.

You can control CS manually with the SPI_CS_CONTROL register.

Hello Octocontrabass,,

i am observing good amount of latency(more than 10us), between subsequent command, i.e what i am trying to tell device does not get ready to transmit another command within in this time, its observed that more the data is previous command more time the device is taking to get ready for the new transmission(i am polling busy bit and fifo empty bits) even with interrupts also i am getting the same delay,, do you have any suggestions(i a have observed similar thing with both PSE and PCH SPI controllers)


Hello Gigasoft,
i am already aware of Software Chip select control,, and tried it before going to Hw Control CS,, issue with that method its adds an additional overhead to the driver + This feature is not available with PSE.


Thanks
Ravi

ravi wrote:its observed that more the data is previous command more time the device is taking to get ready for the new transmission

How much data are you transmitting? What is the clock frequency?

3 bytes of data at ~10mhz, takes about 10us additional time (i.e time between CS going up after transmitting bytes toooooo CS going down again
for the next transmission)

the question may not be clear, i will try to clarify it,,,, the concern is not about how much time it is taking for the data to be transmitted,,

the issue is after the data is transmitted and CS goes High,, the device will only become available to transmit another set of data after 10 us

Are you asking how to insert delays between transmissions? Unfortunately, I didn't see any way to do that in the SPI controller. You'll have to wait for the transmission to complete, then use a timer or counter to measure the delay before you start a new transmission. The SPI controller can notify you with an interrupt, if you don't want to poll it.

i am Sorry Again, the nature of the question is not normal, i will try again

no i am not asking about how to insert delay, in between transmission,


issue i am facing, delay is getting inserted by itself, let me try to explain,

following is simplified sequence

1) CS goes down
2) Data set1 is put on the bus and data transfer complete
3) CS goes up
4) CS goes down
5) Data set2 is put on the bus and data transfer complete
6) CS goes up


Now what is happing is..... between 3) and 4) ~10 us is consumed, some how i cannot reduce the time gap between 3) and 4)

i have tried multiple ways, using PCH controller, Using PSE controller, Using interrupts also more or less same delay is coming, using CS in Hardware control mode, using CS in software control mode(all i do after putting the data on bus is start waiting for the fifo to be empty and device to say its not busy in the status register before i put data set2 on the bus ,,, ) etc.

Some how i am not able to minimize the delay between 3) and 4),,, on other controllers i have worked before its typically less than 1us