Re: The happiest screenshot of my entire OS-dev life!
Posted: Tue Feb 10, 2009 5:21 pm
Hi,
There's a *tad* more than that required...
Cheers,
James
I don't know what you mean by "expect" - surely you're not expecting me to write one for you?blackoil wrote:well, I expect a ASM / C seperated version, that we can share to use in own OS.
No, BAR0 is the MMIO registers, BAR1 is the framebuffer. Always, for nVidia chips, below the GPGPUs, which yours (an NV11) is. PCI knows nothing of the nVidia internal command queue - the DMA buffer is upwards of 1MB large.from PCI32 tool, my gfx card info
Bus 1 (AGP), Device Number 0, Device Function 0
Vendor 10DEh Nvidia Corp
Device 0110h GeForce2 MX/MX 400 [NV11]
Command 0007h (I/O Access, Memory Access, BusMaster)
Status 02B0h (Has Capabilities List, Supports 66MHz, Supports Back-To-Back Tra
s., Medium Timing)
Revision B2h, Header Type 00h, Bus Latency Timer F8h
Minimum Bus Grant 05h, Maximum Bus Latency 01h
Self test 00h (Self test not supported)
PCI Class Display, type VGA
Subsystem ID 009110DEh Unknown
Subsystem Vendor 10DEh Nvidia Corp
Address 0 is a Memory Address (anywhere in 0-4Gb) : FD000000h
Address 1 is a Memory Address (anywhere in 0-4Gb, Prefetchable) : E8000000h
System IRQ 16, INT# A
Expansion ROM of 64Kb decoded by this card (Currently disabled)
New Capabilities List Present:
Power Management Capability, Version 1.1
Does not support low power State D1 or D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)
AGP Capability, Version 2.0 (AGP 4x and below support)
AGP Speed(s) Supported : 1x 2x 4x
FW Transfers Supported : No
>4Gb Address Space Supported : No
Sideband Addressing Supported : No
Maximum Command Queue Length : 32 bytes
AGP Speed Selected : 4x
FW Transfers Enabled : No
>4Gb Address Space Enabled : No
AGP Enabled : Yes
Sideband Addressing Enabled : No
Current Command Queue Length : 32 bytes
address FD000000h is for framebuffer
address E8000000h is for mmio
and PCI32 knows something of FIFO cmd queue.
register map & cmd code are needed to
unlock the engine
put src dest width height colormix in respective registers
then queue cmd code
There's a *tad* more than that required...
Cheers,
James