Yes.JackScott wrote:Using the newer APIC-based interrupt system, I believe the number of hardware interrupts is much higher. I haven't checked though. OSDev wiki will have more information.
There's typically 16 or more IRQs per I/O APIC (for example, there could be one I/O APIC with 24 inputs/IRQs, or a pair of I/O APICs with 16 inputs/IRQs each, or....). The most I've heard of is a system with four I/O APICs. I'm not sure how many inputs each of these I/O APICs had, but with 16 inputs/IRQs per I/O APIC it works out to a total of 64 possible IRQs.
On top of that there's MSI (Message Signaled Interrupts) where a PCI device can send it's IRQ directly over the bus without using any I/O APIC inputs. This means that (for e.g.) if you've got 24 I/O APIC inputs and 8 devices using MSI, then you've got a total of 32 possible IRQs.
The only limit is that interrupt vectors are 8-bit. Given that the first 32 interrupts are reserved for exceptions, this leaves a maximum of 224 IRQs.
However, in theory that limit is "per CPU". With 4 CPUs you could have up to 896 IRQs as long as each IRQ is only ever sent to a specific CPU (and as long as each CPU uses a different IDT). With x2APIC there's a limit of about 4 billion CPUs per computer, so the theoretical maximum for the 80x86 architecture would be about 900 billion IRQs. Note: typically an OS would reserve some interrupt vectors for IPIs (Inter-Processor Interrupts) so the practical limit is a little lower.
Cheers,
Brendan