Is Memory Mapped I/O Taking RAM Address Space for Devices?

[karim]

Does "Memory Mapped I/O" mean, for example, if the CPU is 32-bit (so the address space is 4GB), the BIOS can allocate 3GB of addresses for RAM, and when the BIOS does enumeration, it gives each device (like the graphics card) an address range from the remaining 1GB of addresses?
So basically, the term "Memory Mapped I/O" means that you take part of the address space that could have been used for RAM, but instead you assign it to a device (like the graphics card).
This way, when a program sends an address, the CPU checks if it belongs to RAM or to the graphics card, for example. Is that correct or not?

[Octocontrabass]

Are you sure this isn't you?

[iansjack]

I’m not convinced that a lack of ability, or willingness, to do simple research is a good basis for OS development. Or a good use of other contributors’ time.

Perhaps a book on computer architecture would help.

[sounds]

I am also wary of questions that sound like a CS homework assignment.

[wishedtobe]

Of course it does. Maybe you can find the answer in this document. https://www.intel.com/content/www/us/en ... -of-2.html
If you want to change the DRAM size mapped below 4GB, pay attention to the dword value at the north bridge (Bus 0, Device 0, Function 0) register offset 0xBC.

[robfinch]

It depends on the CPU / MMU. Some CPUs have support for multiple regions or address spaces. The number of address bits is essentially extended by a couple of bits. A CPU may support four regions for instance, MM I/O, RAM/ROM, DDRAM. For a 32-bit CPU each region would have the full address space available, giving the CPU effectively a 34-bit range. In such a CPU/MMU I/O would not be detracting from the amount of space available for RAM. It is typically region bits in the PTEs for the MMU. It is really necessary to read the CPU / MMU docs to find out how address spaces are managed.