Mia Exokernel

[darktemplar]

http://miaexokernel.sourceforge.net/

My kernel is based on segmentation, and portablity on x86 architectures. Kernel itself will be unable to provide any output, because it manages only memory, processor time and multitasking. It's coded in pure asm =)

[earlz]

its about time i saw a segmentation project!

[darktemplar]

Segmentation has some pros I wanted to use, like up to 8192 GB address spaces(and maybe even bigger, no will to calculate it).

[JAAman]

actually, that is 8192 segments (actually 8191, but close enough) of 4GB each for a total of 32TB (1 TB = 1024GB) -- with truely horrible performance (you have to invalidate ALL TLBs on every segment switch (and rewrite the GDT on each segment switch)

and non-segmentation, allows up to 256TB (currently, potentially up to 16EB -- 1EB = 1024PB, 1PB = 1024TB) per address space -- all within a single paging block (meaning no fancy page-manipulation required, and no TLB invalidation, or page rewriting to get to the 'extra' memory)


mabey you have other reasons, but this shouldn't be one of them

[darktemplar]

But paging address space is 4 GB, isn't it? You have user CS, DS, each of 4 GB, so you have 4 GB. And segmentation allows you to have different segments(8191), eg. each 1 GB.

Anyway, If I'm wrong, sorry, I really don't understand that paging. I've seen something like that first time, and I'm like :O how the hell can you get 16 EB in 32-bit addressing?

[earlz]

@darktemplar
thats what i'm thinking

really i prefer paging but i just have wanted to see some os that uses segmentation

are you going to also use segmentation for the kernel or just have it flat

[darktemplar]

Kernel's flat(CS and DS for 4 GB base=0), processes are not

[JAAman]

you will have to use paging to do this right (unless every reference to any segment swaps the entire segment into disk, and a new one out -- you could use partial segments, at variable bases to do this somewhat, but that will get very complicated, very quickly -- esp since segments must be continous) combining with paging will allow you to swap partial segments, but will still require complicated remapping


plus paging will be required to access more than 4GB of physical memory -- very important if you are supporting such large address spaces (all CPUs in the last 10-15 years support 64GB of RAM, rather than 4GB)


paging supports 64bit (though only 52bits are currently useable) addresses -- allowing up to 16EB of address space (in LMode -- currently supported on ALL processors sold by both AMD and Intel -- with the Intel moble being the only exception -- and that will be changing soon)

[darktemplar]

But address space remains still 4 GB. =)
And I don't want to do LMode. I still hang on PMode.

[mrkaktus]

LMode - long mode is thesame like Protected Mode just with 'update' so it support's new features of 64bit processors and break's barrier of 4GB .

(barrier of 4GB is also broken by 36bit adressing with using of extended paging functions on 32bit P4 processors).

To: JAAman - please explain that and tell how it is done because I have newer heard about such thing: "(all CPUs in the last 10-15 years support 64GB of RAM, rather than 4GB) ".

[darktemplar]

I think (all CPUs in the last 10-15 years) support PAE.

[mrkaktus]

I think extremly different :] (386,486 with PAE :> ?)

[JAAman]

386 was released in 1984 -- 22 years ago
486 was released in the late 80s (also well over 15 years ago)

P5 was released in 1991(irrc) -- 15 years ago

the P6 supported PAE and was released over 10 years ago, and became the primary CPU about 2 years later(when the PII was released)

i guess i should have said 10 years, i didnt have my references with me when i posted that last post

but you mentioning the 386/486 is quite out of place, beings that both were out of (general) production more than 13 years ago (intel still makes both for specialized, embeded, markets)