Code: Select all
lea rax, [@f]
lea rcx, [target]
cmp value1, value2
cmova rax, rcx
push rax
mfence
ret
@@:
I believe cmovCC doesn't pair with anything really, but what about condition predition - i don't know.
Code: Select all
lea rax, [@f]
lea rcx, [target]
cmp value1, value2
cmova rax, rcx
push rax
mfence
ret
@@:
I'm not sure how to do that. Intel processors had penalties for not using 4G flat selectors which related to adding the base to form a linear address, which indicates that segmentation checks cannot be skipped with speculative execution. My guess is that Intel would only skjp those checks if 4G flat selectors are used, which both Windows and Linux use.Korona wrote:The issue (for Meltdown) is that those selector CPL vs. PTE checks were not done during speculative execution. I don't know if anyone tested whether segment limit checks are done during speculative execution. So unless that's tested, it's not clear whether segmentation can mitigate the issue or not. (If you test it, feel free to post the results here, would be interesting to know.)
Meltdown is that these checks, which do happen on all CPUs (and which would be a huge bug if they didn't!), happened on the speculative path only to trigger the error if that case was actually executed. They were not used to determine whether to speculate further. That meant that you could leak the data loaded with the invalid load through a side-channel if you have one.Korona wrote:The issue (for Meltdown) is that those selector CPL vs. PTE checks were not done during speculative execution. I don't know if anyone tested whether segment limit checks are done during speculative execution. So unless that's tested, it's not clear whether segmentation can mitigate the issue or not. (If you test it, feel free to post the results here, would be interesting to know.)